Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 988

Universal Serial Bus Interface
Bits Name
7–0 Status
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-60
Table 16-55. qTD Token (DWord 2) (continued)
This field is used by the host controller to communicate individual command execution states back
to the host controller driver (HCD) software. This field contains the status of the last transaction
performed on this qTD. The bit encodings are:
Bits
7 Active. Set by software to enable the execution of transactions by the host
controller.
6 Halted. Set by the host controller during status updates to indicate that a
serious error has occurred at the device/endpoint addressed by this qTD. This
can be caused by babble, the error counter counting down to zero, or
reception of the STALL handshake from the device during a transaction. Any
time that a transaction results in the Halted bit being set, the Active bit is also
cleared.
5 Data buffer error. Set by the host controller during status update to indicate
that the host controller is unable to keep up with the reception of incoming
data (overrun) or is unable to supply data fast enough during transmission
(under run). If an overrun condition occurs, the host controller will force a
time-out condition on the USB, invalidating the transaction at the source. If the
host controller sets this bit to a one, then it remains a one for the duration of
the transfer.
4 Babble detected. Set by the host controller during status update when babble
is detected during the transaction. In addition to setting this bit, the host
controller also sets the Halted bit to a one. Since babble is considered a fatal
error for the transfer, setting the Halted bit to a one insures that no more
transactions occur because of this descriptor.
3 Transaction error (XactErr). Set by the host controller during status update in
the case where the host did not receive a valid response from the device
(time-out, CRC, bad PID). If the host controller sets this bit to a one, then it
remains a one for the duration of the transfer.
2 Missed micro-frame. This bit is ignored unless the QH[EPS] field indicates a
full- or low-speed endpoint and the queue head is in the periodic list. This bit
is set when the host controller detected that a host-induced hold-off caused
the host controller to miss a required complete-split transaction. If the host
controller sets this bit to a one, then it remains a one for the duration of the
transfer.
Description
Status Field Description
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