Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 310

Arbiter and Bus Monitor
Figure 6-6 shows the fields of AEATR.
Offset 0x18
0 4 5
R
—
W
Reset
Table 6-7 describes AEATR fields.
Bits Name
0–4 — Write reserved, read = 0
5–7 EVENT Event type.
000 Address time out
001 Data time out
010 Address only transfer type
011 External control word transfer type
8–10 — Write reserved, read = 0
11–15 MSTR_ID Master Id.
00000 e300 core data transaction
00001 Reserved
00010 e300 core instruction fetch
00011 Reserved
00100 eTSEC1
00101 eTSEC2
00110 Reserved
00111 USB DR
01000 Encryption core
Note: Master Id reflects the source of transaction and is used for debug purpose.
16–19 — Write reserved, read = 0
20 TBST Transfer burst.
0 Burst transaction. Transfer size is greater than 8 bytes
1 Single-beat transaction. Transfer size is up to 8 bytes
21–23 TSIZE Transfer size. Transfer size encoding depends on the value of the field TBST.
TBST = 1:
001 1 byte
010 2 bytes
011 3 bytes
100 4 bytes
101 5 bytes
110 6 bytes
111 7 bytes
000 8 bytes
24–26 — Write reserved, read = 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6-8
7 8 10 11
EVENT — MSTR_ID
Figure 6-6. Arbiter Event Attributes Register (AEATR)
Table 6-7. AEATR Field Descriptions
15 16 19 20 21
— TBST
All zeros
Description
100 Reserved transfer type
101 Transfer error
11 c Reserved
01001 I2C (boot sequencer)
01010 JTAG
01011 Reserved
01100 Reserved
01101 PCI
01110 Reserved
01111 DMA
10000–11111 Reserved
TBST = 0:
000 16 bytes
001 24 bytes
010 32 bytes
011–111 Reserved
Access: User read/write
23 24 26 27
TSIZE — TTYPE
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