Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 932

Universal Serial Bus Interface
Signal
USBDR_PCTL1
USBDR_CLK
16.2.1 UTMI Interface
UTMI was developed to specify a standard interface between USB 2.0 controllers and USB 2.0 PHY's.
This interface is made available to support applications that may use a UTMI-compliant PHY. UTMI+
extensions are not supported by the USB DR module. Functionality added by UTMI+ is available in the
ULPI interface. Only the integrated PHY uses the UTMI interface; therefore, there are no external UTMI
signals to be documented in this manual. The integrated USB PHY has four dedicated external signals,
which are only used when the MPC8313E is a host: USBDR_DRIVE_VBUS, USBDR_PWRFAULT,
USBDR_PCTL0, and USBDR_PCTL1. These signals are also part of ULPI Interface as described below.
16.2.2 ULPI Interface
The ULPI (UTMI low pin count interface) is a reduced pin-count (12 signals) extension of the UTMI+
specification. Pin count is reduced by converting relatively static signals to register bits, and providing a
bidirectional, generic data bus that carries USB and register data. This interface minimizes pin count
requirements for external PHYs.
Signal
USBDR_DIR
USBDR_NXT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-4
Table 16-1. USB External Signals (continued)
I/O
O
I
Table 16-2 describes the signals for the ULPI interface.
Table 16-2. ULPI Signal Descriptions
I/O
I Direction. USBDR_DIR controls the direction of the data bus. When the PHY has data to
transfer to USB port, it drives USBDR_DIR high to take ownership of the bus. When the PHY
has no data to transfer it drives USBDR_DIR low and monitors the bus for link activity. The PHY
pulls USBDR_DIR high whenever the interface cannot accept data from the link.
State Asserted—PHY has data to transfer to the link.
Meaning Negated—PHY has no data to transfer.
Timing Synchronous to PHY_CLK.
I Next data. The PHY asserts USBDR_NXT to throttle the data. When USB port is sending data
to the PHY, USBDR_NXT indicates when the current byte has been accepted by the PHY. The
USB port places the next byte on the data bus in the following clock cycle. When the PHY is
sending data to USB port, USBDR_NXT indicates when a new byte is available for USB port
to consume.
State Asserted—PHY is ready to transfer byte.
Meaning Negated—PHY is not ready.
Timing Synchronous to PHY_CLK.
ULPI—Use as USBDR_PCTL1USB_VDDA
ULPI—Use as USBDR_CLK
Description
Description
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