Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 925

Table 15-176. RTBI Mode Register Initialization Steps (continued)
15.7.1.5 SGMII Interface Support
Signals
TX n /TX n
RX n /RX n
SGMII mode initialization sequence is very similar to TBI mode initialization. Additional initialization is
required for the SerDes. An example of SGMII mode initialization sequence is shown in
SGMII mode utilizes the internal TBI PHY. The internal TBI PHY only
auto-negotiates at 1 Gbps. However, 10 Mbps and 100 Mbps speeds are
supported in SGMII mode. It is recommended that the external PHY inform
the MAC if the desired link speed is not 1 Gbps. Software can perform MII
management cycles to determine the external PHY link speed and program
ECNTRL and MACCFG2 accordingly.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize DMACTRL (Optional)
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Initialize TBASE0–TBASE7,
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize RBASE0–RBASE7,
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Enable Transmit Queues
Initialize TQUEUE
Enable Receive Queues
Initialize RQUEUE
Enable Rx and Tx,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
Table 15-177. SGMII Interface Signal Configuration (4-Wire)
SerDes Signals
Frequency [MHz] 1250
Voltage [V] LVDS
No. of
I/O
Signals
O
I
Sum
SGMII Interface
Frequency [MHz] 1250
Voltage [V] LVDS
Signals
2 TXD
2 RXD
4 Sum
NOTE
Enhanced Three-Speed Ethernet Controllers
No. of
I/O
Signals
O 2
I 2
4
Table 15-178.
15-207