Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 628

PCI Bus Interface
13.4.2 Bus Commands
PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on
PCI_C/BE[3:0] during the address phase of the transaction. PCI bus commands are described in
Table 13-45.
PCI_C/
Command Type
BE[3:0]
0b0000 Interrupt acknowledge
0b0001 Special cycle
0b0010 I/O read
0b0011 I/O write
0b010x —
0b0110 Memory read
0b0111 Memory write
0b100x —
0b1010 Configuration read
0b1011 Configuration write
0b1100 Memory read multiple
0b1101 Dual address cycle
0b1110 Memory read line
Memory write and
0b1111
invalidate
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-46
Table 13-45. PCI Command Definitions
Supported as:
Initiator Target
A read implicitly addressed to the system interrupt controller. The size of
Yes No the vector to be returned is indicated on the byte enables after the
address phase.
Provides a simple message broadcast mechanism. See
Yes No
Section 13.4.4.6, "Special Cycle Command,"
Yes No Accesses agents mapped in I/O address space.
Yes No Accesses agents mapped in I/O address space.
— — Reserved. No response occurs.
Accesses agents mapped in memory address space. A read from
prefetchable space, when seen as a target, fetches a cache line of data
Yes Yes
(32 bytes) from the starting address, even though all 32 bytes may not
actually be sent to the initiator.
Accesses agents mapped in memory address space. Note that for
inbound writes less than 4-bytes, the PCI controller splits the transaction
Yes Yes into single byte writes to the target. Thus, the PCI interface cannot be
used to perform single beat writes to 16-bit devices on the local
peripheral interfaces.
— — Reserved. No response occurs.
Accesses the configuration space of each agent. An agent is selected
when its IDSEL signal is asserted. See
Yes Yes Configuration Access,"
As a target, a configuration read is only accepted if the PCI controller is
configured to be in agent mode.
Accesses the configuration space of each agent. An agent is selected
when its IDSEL signal is asserted. See
Yes Yes Configuration Access,"
write is only accepted if the PCI controller is configured to be in agent
mode.
Yes Yes Causes a prefetch of the next cache line.
No Yes Transfers an 8-byte address to devices.
Yes Yes Indicates that the initiator intends to transfer an entire cache line of data.
Indicates that the initiator will transfer an entire cache line of data, and if
No Yes
PCI has any cacheable memory, this line needs to be invalidated.
Definition
for more information.
Section 13.4.4.4, "Host Mode
for more information on configuration accesses.
Section 13.4.4.4, "Host Mode
for more information. As a target, a configuration
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