Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 443

9.6 Initialization/Application Information
System software must configure the DDR memory controller, using a memory polling algorithm at system
start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths.
System software must also configure the DDR memory controller at system start-up to appropriately
multiplex the row and column address bits for each bank. Refer to row-address configuration in
Section 9.4.1.2, "Chip Select Configuration (CSn_CONFIG)."
these configuration bits.
At system reset, initialization software (boot code) must set up the programmable parameters in the
memory interface configuration registers. See
descriptions of the configuration registers. These parameters are shown in
Table 9-34. Memory Interface Configuration Register Initialization Parameters
Name
CS n _BNDS
CS n _CONFIG
TIMING_CFG_3
TIMING_CFG_0
TIMING_CFG_1
TIMING_CFG_2
DDR_SDRAM_CFG
DDR_SDRAM_CFG_2
DDR_SDRAM_MODE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Section 9.4.1, "Register Descriptions,"
Description
Chip select memory bounds
Chip select configuration
Extended timing parameters for
fields in TIMING_CFG_1
Timing configuration
Timing configuration
Timing configuration
Control configuration
Control configuration
Mode configuration
Address multiplexing occurs according to
Table
Parameter
SA n
EA n
CS_ n _EN BA_BITS_CS_ n
AP_ n _EN ROW_BITS_CS_ n
COL_BITS_CS_ n
ODT_RD_CFG
ODT_WR_CFG
EXT_REFREC
RWT ACT_PD_EXIT
WRT PRE_PD_EXIT
RRT ODT_PD_EXIT
WWT MRS_CYC
PRETOACT REFREC
ACTTOPRE WRREC
ACTTORW ACTTOACT
CASLAT WRTORD
ADD_LAT WR_DATA_DELAY
CPO CKE_PLS
WR_LAT FOUR_ACT
RD_TO_PRE
SREN NCAP
RD_EN 2T_EN
SDRAM_TYPE BA_INTLV_CTL
DYN_PWR x32_EN
32_BE
8_BE
DBW
DQS_CFG NUM_PR
ODT_CFG D_INIT
ESDMODE
SDMODE
DDR Memory Controller
for more detailed
9-34.
Section/Page
9.4.1.1/9-9
9.4.1.2/9-10
9.4.1.3/9-11
9.4.1.4/9-12
9.4.1.5/9-14
9.4.1.6/9-16
9.4.1.7/9-18
HSE
BI
9.4.1.8/9-21
9.4.1.9/9-22
9-49