Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 483

Bits Name
23 ECCM ECC mode. When hardware checking and/or generation of error correcting codes (ECC) is enabled
(that is, when BR n [DECC] is 01 or 10, and full page transfers are specified with FBCR[BC] = 0), ECCM
sets the ECC block size and position of the ECC code word(s) in the NAND Flash spare region for both
checking and generation functions. The format of the ECC code word conforms with the
Samsung/Toshiba spare region assignment specifications.
0 ECC is checked/calculated over 512-Byte blocks. A 24-bit ECC is assigned to spare region bytes at
offsets ( N ×16)+6 through ( N ×16)+8 for spare region N , N = 0–3.
1 ECC is checked/calculated over 512-Byte blocks. A 24-bit ECC is assigned to spare region bytes at
offsets ( N ×16)+8 through ( N ×16)+10 for spare region N , N = 0–3.
24–25 — Reserved
26–27 AL Address length. AL sets the number of address bytes issued during page address (PA) operations.
However, the number of address bytes issued for column address (CA) operations is determined by
the device page size (for OR n [PGS] = 0, 1 CA byte is issued; for OR n [PGS] = 1, 2 CA bytes are issued).
00 2 bytes are issued for page addresses, thus a total of 3 (OR n [PGS] = 0) or 4 (OR n [PGS] = 1)
address bytes are issued for a {CA,PA} sequence
01 3 bytes are issued for page addresses, thus a total of 4 (OR n [PGS] = 0) or 5 (OR n [PGS] = 1)
address bytes are issued for a {CA,PA} sequence
10 4 bytes are issued for page addresses, thus a total of 5 (OR n [PGS] = 0) or 6 (OR n [PGS] = 1)
address bytes are issued for a {CA,PA} sequence
11 —
28–29 — Reserved
30–31 OP Flash operation. For OP not equal to 00, a special operation is triggered on the next write to LSOR or
dummy access to a bank controlled by FCM. Once a special operation has commenced, OP is
automatically reset to 00 by FCM. Individual blocks may be temporarily unlocked for erase and
reprogramming operations.
00 Normal operation. All read and write accesses to banks controlled by FCM access the shared FCM
buffer RAM. No bus activity is caused by this operation.
01 Simulate auto-boot block loading, and set FMR[BOOT]. Boot block loading occurs from the bank
triggered on the special operation, therefore the appropriate bank configuration must be initialized
prior to issuing this operation.
10 Execute the command sequence contained in FIR, but with write protection enabled (pin LFWP
asserted low) so that all Flash blocks are protected from accidental erasure and reprogramming.
11 Execute the command sequence contained in FIR, but permit the single block identified by
FBAR[BLK] to be erased or reprogrammed, with pin LFWP remaining high during the access.
10.3.1.18 Flash Instruction Register (FIR)
The local bus Flash instruction register (FIR), shown in
instructions for issue by the FCM. Setting FMR[OP] non-zero and writing LSOR or accessing a bank
controlled by FCM causes FCM to read FIR 4 bits at a time, starting at bit 0 and continuing with adjacent
4-bit opcodes, until only NOP opcodes remain. The programmed instruction sequence of OP0, OP1,...,
OP7 is performed on the activated bank, using the data buffer addressed by FPAR. If LTEIR[CCI] = 1 and
LTEDR[CCD] = 0, eLBC will generate an interrupt once the entire sequence has completed, and software
should examine LTEATR and clear its V bit.
Software must not alter the contents of the addressed FCM buffer, FIR, MDR, FCR, FBAR, FPAR, or
FBCR while an operation is in progress—or eLBC will behave unpredictably—but software can freely
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-24. FMR Field Descriptions (continued)
Description
Figure 10-22, holds a sequence of up to eight
Enhanced Local Bus Controller
10-35