Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 977

16.5.2 Asynchronous List Queue Head Pointer
The asynchronous transfer list (based at the ASYNCLISTADDR register) is where all the control and bulk
transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the
periodic list is disabled, or the periodic list is empty.
AsyncListAddr
The asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply
a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked
into the asynchronous list.
16.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)
Figure 16-38 illustrates the format of an isochronous transfer descriptor. This structure is used only for
high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs
must be aligned on a 32-byte boundary.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-39. Typ Field Encodings
Typ
00 Isochronous transfer descriptor
01 Queue head
10 Split transaction isochronous transfer descriptor
11 Frame span traversal node
Operational
Registers
Figure 16-37. Asynchronous Schedule Organization
Description
Bulk/Control Queue Heads
H
Universal Serial Bus Interface
16-49