Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 22

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Number
14.4.2.13 MDEU FIFOs ...................................................................................................... 14-40
14.4.3 Advanced Encryption Standard Execution Unit (AESU)........................................ 14-40
14.4.3.1 AESU Mode Register (AESUMR)...................................................................... 14-40
14.4.3.2 AESU Key Size Register (AESUKSR) ............................................................... 14-42
14.4.3.3 AESU Data Size Register (AESUDSR) .............................................................. 14-43
14.4.3.4 AESU Reset Control Register (AESURCR) ....................................................... 14-43
14.4.3.5 AESU Status Register (AESUSR)....................................................................... 14-44
14.4.3.6 AESU Interrupt Status Register (AESUISR)....................................................... 14-45
14.4.3.7 AESU Interrupt Control Register (AESUICR).................................................... 14-47
14.4.3.8 AESU End-of-Message Register (AESUEMR) .................................................. 14-48
14.4.3.9 AESU Context Registers ..................................................................................... 14-49
14.4.3.9.1
14.4.3.9.2
14.4.3.9.3
14.4.3.9.4
14.4.3.9.5
14.4.3.9.6
14.5 Channel ........................................................................................................................ 14-53
14.5.1 Channel Registers .................................................................................................... 14-55
14.5.1.1 Crypto-Channel Configuration Register (CCCR) ............................................... 14-55
14.5.1.2 Crypto-Channel Pointer Status Register (CCPSR).............................................. 14-57
14.5.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPR) ........................... 14-62
14.5.1.4 Fetch FIFO (FF)................................................................................................... 14-62
14.5.1.5 Descriptor Buffer (DB)........................................................................................ 14-63
14.5.2 Channel Interrupts.................................................................................................... 14-64
14.5.2.1 Channel Done Interrupt ....................................................................................... 14-64
14.5.2.2 Channel Error Interrupt........................................................................................ 14-64
14.5.2.3 Channel Reset ...................................................................................................... 14-64
14.6 Controller ..................................................................................................................... 14-64
14.6.1 Assignment of EUs to Channel................................................................................ 14-65
14.6.2 Bus Interface ............................................................................................................ 14-65
14.6.2.1 Arbitration for Use of the Controller and Buses.................................................. 14-65
14.6.2.2 Master Read ......................................................................................................... 14-66
14.6.2.3 Master Write ........................................................................................................ 14-66
14.6.3 Controller Interrupts ................................................................................................ 14-66
14.6.4 Controller Registers ................................................................................................. 14-67
14.6.4.1 EU Assignment Status Register (EUASR) .......................................................... 14-67
14.6.4.2 Interrupt Mask Register (IMR)............................................................................ 14-68
14.6.4.3 Interrupt Status Register (ISR) ............................................................................ 14-70
14.6.4.4 Interrupt Clear Register (ICR) ............................................................................. 14-71
14.6.4.5 Identification Register (ID).................................................................................. 14-73
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
xxii
Contents
Context for CBC Mode.................................................................................... 14-50
Context for Counter Mode............................................................................... 14-50
Context for SRT Mode .................................................................................... 14-50
Context for CCM Mode................................................................................... 14-50
AESU Key Registers ....................................................................................... 14-53
AESU FIFOs.................................................................................................... 14-53
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Freescale Semiconductor