Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 847

Bits Name
7–8 Pause Encoding of the link partner's PAUSE capability is shown in the PAUSE encoding table below. For priority
resolution information consult. This bit is read-only
PAUSE bit[8]
9 Half Half-duplex capability. This bit is read-only.
Duplex 0 Link partner is not capable of half-duplex mode.
1 Link partner is capable of half-duplex mode.
10 Full Full-duplex capability. This bit is read-only.
Duplex 0 Link partner is not capable of full-duplex mode.
1 Link partner is capable of full-duplex mode.
11–15 — Reserved, should be cleared.
15.5.4.3.5 AN Expansion Register (ANEX)
Figure 15-121 describes the definition for the ANEX register.
Offset 0x06
0
R
W
Reset
Table 15-131 describes the fields of the ANEX register.
Bits Name
0–12 — Reserved, should be cleared.
13 NP Next page able. This bit is read-only and returns 1 on read. While read as set, indicates local device supports
Able next page function.
14 Page Page received. This bit is read-only. The bit clears on a read to the register.
Rx'd 0 Normal operation.
1 A new page was received and stored in the applicable AN link partner ability or AN next page register. This
bit latches high in order for software to detect while polling.
15 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-130. ANLPBPA Field Descriptions (continued)
ASM_DIR bit[7]
0 0
0 1
1 0
1 1
—
Figure 15-121. AN Expansion Register Definition
Table 15-131. ANEX Field Descriptions
Description
Capability
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read only
12 13
NP Able Page Rx'd
14 15
—
15-129