Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 14

Paragraph
Number
9.6 Initialization/Application Information ........................................................................... 9-49
9.6.1 Programming Differences Between Memory Types.................................................. 9-50
9.6.2 DDR SDRAM Initialization Sequence ...................................................................... 9-53
10.1 Introduction.................................................................................................................... 10-1
10.1.1 Overview.................................................................................................................... 10-2
10.1.2 Features...................................................................................................................... 10-2
10.1.3 Modes of Operation ................................................................................................... 10-3
10.1.3.1 eLBC Bus Clock and Clock Ratios ....................................................................... 10-3
10.1.3.2 Source ID Debug Mode ......................................................................................... 10-4
10.2 External Signal Descriptions ......................................................................................... 10-4
10.3 Memory Map/Register Definition ................................................................................. 10-7
10.3.1 Register Descriptions................................................................................................. 10-9
10.3.1.1 Base Registers (BR0–BR3) ................................................................................... 10-9
10.3.1.2 Option Registers (OR0–OR3).............................................................................. 10-11
10.3.1.2.1
10.3.1.2.2
10.3.1.2.3
10.3.1.2.4
10.3.1.3 UPM Memory Address Register (MAR)............................................................. 10-19
10.3.1.4 UPM Mode Registers (MxMR) ........................................................................... 10-20
10.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 10-22
10.3.1.6 UPM/FCM Data Register (MDR) ....................................................................... 10-22
10.3.1.7 Special Operation Initiation Register (LSOR)..................................................... 10-23
10.3.1.8 UPM Refresh Timer (LURT)............................................................................... 10-24
10.3.1.9 Transfer Error Status Register (LTESR) .............................................................. 10-25
10.3.1.10 Transfer Error Check Disable Register (LTEDR)................................................ 10-27
10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR) .............................................. 10-28
10.3.1.12 Transfer Error Attributes Register (LTEATR) ..................................................... 10-29
10.3.1.13 Transfer Error Address Register (LTEAR).......................................................... 10-30
10.3.1.14 Transfer Error ECC Register (LTECCR)............................................................. 10-30
10.3.1.15 Local Bus Configuration Register (LBCR) ......................................................... 10-31
10.3.1.16 Clock Ratio Register (LCRR).............................................................................. 10-33
10.3.1.17 Flash Mode Register (FMR)................................................................................ 10-34
10.3.1.18 Flash Instruction Register (FIR) .......................................................................... 10-35
10.3.1.19 Flash Command Register (FCR) ......................................................................... 10-36
10.3.1.20 Flash Block Address Register (FBAR)................................................................ 10-37
10.3.1.21 Flash Page Address Register (FPAR) .................................................................. 10-37
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
xiv
Contents
Enhanced Local Bus Controller
Address Mask .................................................................................................. 10-11
Option Registers (ORn)—GPCM Mode ......................................................... 10-13
Option Registers (ORn)—FCM Mode ............................................................ 10-15
Option Registers (ORn)—UPM Mode ............................................................ 10-18
Title
Chapter 10
Page
Number
Freescale Semiconductor