Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 845

Bits Name
4–6 — Reserved, should be cleared.
7–8 Pause The local device's PAUSE capability is encoded in bits 7 and 8, and the decodes are shown in the following
table. For priority resolution information consult
PAUSE bit[8]
9 Half Half-duplex capability.
Duplex 0 Designates local device as not capable of half-duplex operation.
1 Designates local device as capable of half-duplex operation.
10 Full Full-duplex capability.
Duplex 0 Designates the local device as not capable of full-duplex operation.
1 Designates the local device as capable of full-duplex operation.
11–15 — Reserved, should be cleared.
Table 15-129 describes the resolution of pause priority.
Local Device
PAUSE ASM_DIR
0 0
0 1
0 1
0 1
1 0
1 0
1 1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-128. ANA Field Descriptions (continued)
ASM_DIR bit[7]
0 0
0 1
1 0
1 1
Table 15-129. PAUSE Priority Resolution
Link Partner
PAUSE ASM_DIR
x x
0 x
1 0
1 1
0 x
1 x
0 0
Description
Table 15-129.
Capability
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
Local Resolution
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Enable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Enable PAUSE transmit
Enable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Enhanced Three-Speed Ethernet Controllers
Link Partner Resolution
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Enable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Enable PAUSE transmit
Enable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
15-127