Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 601

Bits Name
8–9 — Reserved
10–11 TS Transaction size. Indicates the size of the transaction in units of doublewords (8 bytes). If the transaction
crossed a cache line (32-byte) boundary, this field indicates the number of actual double words in the cache
line on which the error occurred. This field is valid only if the PCI controller was the master of the
transaction.
00 4 double words
01 1 double word
10 2 double words
11 3 double words
12–15 ES Error source. This field indicates the source of the PCI transaction.
0000 External master
0101 DMA
Others reserved
16–19 CMD PCI command. Contains the PCI command PCI_CBE[3:0] of the transaction.
20–23 — Reserved
24–27 BE PCI byte enables. Contains the PCI byte enables PCI_CBE[3:0] for the data word.
28–29 — Reserved
30 PB Parity bit. Contains the PCI parity bit for the captured data word.
31 VI Error information valid. This bit indicates that the error information captured in this register, PCI_EACR,
PCI_EEACR, and PCI_EDCR is valid.
0 No valid error information
1 Error information is valid
13.3.2.5 PCI Error Address Capture Register (PCI_EACR)
PCI_EACR contains fields for storing the low portion of the address associated with the first PCI error
captured. Figure 13-9
Offset 0x10
0
R
W
Reset
Table 13-12 describes the bit settings of the PCI_EACR register.
Bits Name
0–31 PCI_EA
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 13-11. PCI_EATCR Field Descriptions (continued)
shows the PCI_EACR fields.
Figure 13-9. PCI Error Address Capture Register (PCI_EACR)
Table 13-12. PCI_EACR Field Description
PCI error address. Contains the low portion of the address associated with the first detected error.
Read only.
Description
PCI_EA
All zeros
Description
PCI Bus Interface
Access: Read only
31
13-19