Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 516

Enhanced Local Bus Controller
LFCLE
long-latency CW command issue
LFWE
LFRB
TRLX = 0:
TRLX = 1:
LFRE
10.4.3.3.4 FCM Read Data Timing
The timing for read data transfers is shown in
enable its output drivers and drive valid read data while LFRE is held low. FCM samples read data on the
rising edge of LFRE, which follows an optional number of wait states. Note that FCM will delay the first
read if a RBW or RSW instruction is issued, in which case LFRB sample timing takes effect (see
Section 10.4.3.3.3, "FCM Ready/Busy
LCLK
(unused)
LFWE
write cycle
LFCLE/
LFALE
LFRE
LAD[0:7] write data
TA
Notes:
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-68
LFRB sample
8×(2+SCY) cycles
16×(2+SCY) LCLK cycles
Figure 10-54. FCM Delay Prior to Sampling LFRB State
Figure
Timing").
write-to-read turnaround
t
t = LFRE pulse time, read period.
RP
t = LFRE hold time.
RHT
t = Write to read turnaround time.
WRT
Figure 10-55. FCM Read Data Timing
(for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N)
NAND FlashFlash busy state
points
10-55. Upon assertion of LFRE, the Flash device will
WRT
t = Read wait state time.
WS
t = Read data cycle time.
RC
ready state
FCM continues
following LFRB high
read cycle
t
RHT
t
RP
t
WS
t
RC
read data
sample data
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