Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 669

Bits Name
59 IFE Input FIFO error. The shared symmetric input FIFO was detected non-empty upon generation of done
interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
60 IFU Input FIFO underflow. The shared symmetric input FIFO has been read while empty.
0 Input FIFO underflow error enabled
1 Input FIFO underflow error disabled
61 IFO Input FIFO overflow. The shared symmetric input FIFO has been pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Note: When operated through channel-controlled access, SEC implements flow control, and FIFO size is not
a limit to data input. When operated through host-controlled access, the DEU cannot accept FIFO
inputs larger than 256 bytes without overflowing.
62 OFU Output FIFO underflow. The shared symmetric output FIFO has been read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
63 OFO Output FIFO overflow. The shared symmetric output FIFO has been pushed while full.
0 Output FIFO overflow error enabled
1 Output FIFO overflow error disabled
14.4.1.8 DEU End-of-Message Register (DEUEMR)
The DEU end-of-message register (DEUEMR), shown in
completed. After the final message block is written to the input FIFO, the DEUEMR must be written. The
value in the data size register will be used to determine how many bits of the final message block (always
64) will be processed. Note that this register has no data size, and during the write operation, the host data
bus is not read. Hence, any data value is accepted. Normally, a write operation with a zero data value is
performed. Moreover, no read operation from this register is meaningful, but no error is generated, and a
zero value is always returned. Writing to the DEUEMR is merely a trigger causing the DEU to process the
final block of a message, allowing it to signal DONE.
0
Field
Reset
R/W
Addr
14.4.1.9 DEU IV Register (DEUIV)
For CBC mode, the initialization vector is written to and read from the DEU IV register (DEUIV). The
value of this register changes as a result of the encryption process and reflects the context of the DEU.
Reading this memory location while the module is processing data generates an error interrupt.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 14-16. DEUICR Field Descriptions (continued)
Figure 14-14. DEU End-of-Message Register (DEUEMR)
Description
Figure 14-14, indicates a DES operation may be
DEU End-of-Message
0
W
DEU 0x3_2050
Security Engine (SEC) 2.2
63
14-27