Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 852

Enhanced Three-Speed Ethernet Controllers
Table 15-136 describes the fields of the TBICON register.
Bits Name
0 Soft_Reset Soft reset. This bit is cleared by default.
0 Normal operation.
1 Resets the functional modules in the TBI.
1 — Reserved. (Ignore on read)
2 Disable Rx Dis Disable receive disparity. This bit is cleared by default.
0 Normal operation.
1 Disables the running disparity calculation and checking in the receive direction.
3 Disable Tx Dis Disable transmit disparity. This bit is cleared by default.
0 Normal operation.
1 Disables the running disparity calculation and checking in the transmit direction.
4–6 — Reserved
7 AN Sense Auto-negotiation sense enable. This bit is cleared by default.
0 IEEE 802.3z Clause 37 behavior is desired, which results in the link not completing.
1 Allow the auto-negotiation function to sense either a Gigabit MAC in auto-negotiation bypass mode
8–9 — Reserved
10 Clock Select Clock select. This bit is cleared by default.
0 Allow the TBI to accept dual split-phase 62.5 MHz receive clocks.
1 Configure the TBI to accept a 125 MHz receive clock from the SerDes/PHY. The 125 MHz clock must
11 MI Mode This bit describes the configuration mode of the TBI. The user reads a 1 while the TBI is configured in
GMII/MII mode (connected to a GMII/MII PHY) and a 0 while configured in TBI mode (connected to a
1000BASE-X SerDes). Its value is the inverse of ECNTRL[TBIM].
0 TBI mode.
1 GMII mode.
12–15 — Reserved
15.6 Functional Description
15.6.1 Connecting to Physical Interfaces on Ethernet
This section describes how to connect the eTSEC to various interfaces: MII, RMII, RGMII, and RTBI. To
avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3 specification because
the PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[3:0], bit 3 is the msb and
bit 0 is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that
are not used must be pulled low on the board.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-134
Table 15-136. TBICON Field Descriptions
or an older Gigabit MAC without auto-negotiation capability. If sensed, auto-negotiation complete
becomes true; however, the page received is low, indicating no page was exchanged. Management
can then act accordingly.
be physically connected to 'PMA receive clock 0' if using a parallel (non-SGMII) Ethernet protocol.
Description
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