Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 808

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.22 Receive Fragments Counter (RFRG)
Figure 15-73 describes the definition for the RFRG register.
Offset eTSEC1:0x2_46D4; eTSEC2:0x2_56D4
0
R
W
Reset
Table 15-77 describes the fields of the RFRG register.
Bits Name
0–15 — Reserved
16–31 RFRG Receive fragments counter. Increments for each frame received which is less than 64 bytes in length and
contains an invalid FCS. This includes integral and non-integral lengths.
15.5.3.6.23 Receive Jabber Counter (RJBR)
Figure 15-74 describes the definition for the RJBR register.
Offset eTSEC1:0x2_46D8; eTSEC2:0x2_56D8
0
R
W
Reset
Table 15-78 describes the fields of the RJBR register.
Bits Name
0–15 — Reserved
16–31 RJBR Receive jabber counter. Increments for frames received which exceed 1518 (non VLAN) or 1522 (VLAN)
bytes and contain an invalid FCS. This includes alignment errors.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-90
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Figure 15-73. Receive Fragments Counter Register Definition
Table 15-77. RFRG Field Descriptions
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Figure 15-74. Receive Jabber Counter Register Definition
Table 15-78. RJBR Field Descriptions
15 16
All zeros
Description
15 16
All zeros
Description
Access: Read/Write
RFRG
Access: Read/Write
RJBR
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