Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 598

PCI Bus Interface
Table 13-8 describes the bit settings of the PCI_ESR register.
Bits Name
0 MERR
1–20 —
21 APAR
22 PCISERR PCI system error.Set when the PCI_SERR input signal is asserted. See
23 MPERR
24 TPERR
25 NORSP
26 TABT
27–31 —
13.3.2.2 PCI Error Capture Disable Register (PCI_ECDR)
PCI_ECDR contains fields for controlling the capture of the transaction that caused an error. Each bit
corresponds to the error condition reported in the PCI error status register (PCI_ESR). Note that only the
first error is captured, so disabling the capture of some error types may allow greater visibility of the
significant errors.
• 1 = Do not capture the transaction that caused this error.
• 0 = Capture the transaction that caused this error.
Figure 13-6 shows the PCI_ECDR fields.
Offset 0x04
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Table 13-8. PCI_ESR Field Descriptions
Multiple errors. Set if any other bit of this register is 1 and the same error type occurs again.
Reserved
Address parity error. Set when there is an address parity error on a PCI access initiated by a device
other than this PCI controller.
information on PCI_SERR.
Master parity error. Set when the PCI_PERR input signal is asserted on a write access initiated by
this PCI controller or when a data parity error is detected by this PCI controller on a read access that
it initiated.
Target parity error. Set when this PCI controller is the target of a transaction and the PCI_PERR input
signal is asserted on a read access or a data parity error is detected by this PCI controller on a write
access.
No response. Set when there is no response to a transaction initiated by this PCI controller on the
PCI bus (no PCI_DEVSEL assertion).
Target abort. Set when a PCI target abort occurs on a transaction initiated by this PCI controller.
Reserved
20
—
Figure 13-6. PCI Error Capture Disable Register (PCI_ECDR)
Description
21 22 23
APAR PCISERR MPERR TPERR NORSP TABT
All zeros
Table 13-3 for more
Access: Read/Write
24 25 26 27
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