Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 331

— The performance monitor local control registers (PMLCa0–PMLCa3) control each individual
performance monitor counter. Each counter has a corresponding PMLCa register.
UPMLCa0–UPMLCa3 provide user-level read access to PMLCa0–PMLCa3).
• The performance monitor interrupt is assigned to interrupt vector 0x0F00.
Software communication with the performance monitor is achieved through PMRs rather than SPRs. The
PMRs are used for enabling conditions that can trigger the performance monitor interrupt.
7.2 PowerPC Architecture Implementation
The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can
be measured in terms of which of the following levels of the architecture is implemented:
• User instruction set architecture (UISA)—Defines the base user-level instruction set, user-level
registers, data types, floating-point interrupt model, memory models for a uniprocessor
environment, and programming model for a uniprocessor environment.
• Virtual environment architecture (VEA)—Describes the memory model for a multiprocessor
environment, defines cache control instructions, and describes other aspects of virtual
environments. Implementations that conform to the VEA also adhere to the UISA but may not
necessarily adhere to the OEA.
• Operating environment architecture (OEA)—Defines the memory management model,
supervisor-level registers, synchronization requirements, and interrupt model. Implementations
that conform to the OEA also adhere to the UISA and VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and core interface
implementations.
7.3 Implementation-Specific Information
This section describes the PowerPC architecture in general and specific details about the implementation
of the e300 core as a low-power, 32-bit member of this PowerPC core family. The main topics addressed
are as follows:
• Section 7.3.1, "Register Model,"
common among e300 cores that implement the PowerPC architecture and describes the
programming model. It also describes the additional registers that are unique to the core.
• Section 7.3.2, "Instruction Set and Addressing Modes,"
addressing modes for the OEA, and defines and describes the instructions implemented in the core.
• Section 7.3.3, "Cache Implementation,"
cores that implement the PowerPC architecture by the VEA. It also provides specific details about
the e300 core cache implementation.
• Section 7.3.4, "Interrupt Model,"
the core interrupt model.
• Section 7.3.5, "Memory Management,"
management among these cores. This section also describes the core implementation of the 32-bit
PowerPC memory management specification.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
describes the registers for the operating environment architecture
describes the cache model that is defined generally for
describes the interrupt model of the OEA and the differences in
describes generally the conventions for memory
e300 Processor Core Overview
describes the PowerPC instruction set and
7-13