Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 957

Bits Name
8 PR Port reset.
Host mode:
• When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision
2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
duration is timed in the driver.
Device mode:
• This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
1 Port is in reset.
0 Port is not in reset.
This field is zero if Port Power(PP) is zero.
7 SUSP Suspend.
Host mode:
• The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows:
0x Disable
10 Enable
11 Suspend
• When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not
change until the port is suspended and that there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
• The module unconditionally sets this bit to zero when software clears the FPR bit. A write of zero to this bit
is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (that is,
port enabled bit is a zero) the results are undefined.
• This field is zero if Port Power (PP) is zero in host mode.
Device mode:
1 Port in suspend state.
0 Port not in suspend state. Default.
In device mode this bit is a read-only status bit.
6 FPR Force port resume. This bit is not-EHCI compatible.
1 Resume detected/driven on port.
0 No resume (K-state) detected/driven on port.
Host mode:
• Software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition
is detected while the port is in the Suspend state. When this bit transitions to a one a J-to-K transition is
detected, USBSTS[PCI] (port change detect) is also set. This bit will automatically change to zero after the
resume sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the resume duration is timed in the driver.
• Note that when the controller owns the port, the resume sequence follows the defined sequence
documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the
port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed
idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the
port control state switches to HS or FS idle.
• This field is zero if Port Power (PP) is zero in host mode.
Device mode:
• After the device has been in Suspend State for 5 msec or more, software must set this bit to one to drive
resume signaling before clearing. The USB DR controller will set this bit to one if a J-to-K transition is
detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal
operation. Also, when this bit transitions to a one because a J-to-K transition detected, USBSTS[PCI] is also
set.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-29