Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 519

Figure 10-57. FCM Buffer RAM Memory Map During Boot Loading
The process for booting is as follows:
1. Following negation of PORESET, eLBC is released from reset and commences automatic boot
block loading if FCM is selected as the boot ROM location. Small-page or large-page, 8-bit NAND
Flash devices can be used for boot loading when enabled with LCS0. eLBC drives LFWP low
during boot accesses to prevent accidental erasure of the NAND Flash boot ROM.
2. FCM starts searching for a valid boot block at block index 0.
3. FCM reads the spare regions of the first two pages of the current block, checking the bad block
indication (BI) bytes to validate the block for reading. BI bytes must all hold the value 0xFF for
the page to be considered readable.
— For small-page devices, BI is a single byte read from spare region byte offset 5.
— For large-page devices, BI is a single byte read from spare region byte offset 0.
If either of the first two pages of the current block are marked invalid, then the boot block index is
incremented by 1, and FCM repeats step 3. eLBC will continue searching for a bootable block
indefinitely, therefore at least one block must be marked valid for boot loading to proceed. At the
conclusion of the boot block search, the value of FBAR[BLK] points to the boot block.
4. If ECC checking is enabled, the FCM recovers from the spare region the stored ECC for each
512-byte block of boot data. The boot block must be prepared with ECC protection. During ECC
generation, software should use FMR[ECCM] = 0 for small-page devices, and FMR[ECCM] = 1
for large-page devices.
If RCW initialization is required, the first 64 bytes of the boot block must be prepared in
accordance with the layout described in
5. FCM performs a sequence of random-access page reads, reading entire pages from the boot block
until 4 Kbytes have been saved to the FCM buffer RAM. If ECC checking is enabled, the ECC of
each 512-byte region is verified and single-bit errors are corrected if possible. If FCM is unable to
correct ECC errors, eLBC halts the boot process and signals an unrecoverable error by asserting
the hreset_req signal.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Bank Base Address
boot block buffer
offset 0x1000
replicated FCM
buffer RAM
images in bank
End of Bank
4096-byte boot block
—no NAND Flash spare regions
Section 4.3.3.1.1, "Local Bus Controller
Enhanced Local Bus Controller
Setting."
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