Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 270

System Configuration
5.7.6 Functional Description
5.7.6.1 General-Purpose Timer Units
The clock input to the timer's prescaler can be selected from the following sources:
• The system clock
• The system slow go clock (internally divided by 16)
The general system clock is generated in the clock synthesizer and defaults to the system frequency.
However, the general system clock has the option to be divided before it leaves the clock synthesizer. This
mode, called slow go, is used to save power. Whatever the resulting frequency of the general system clock,
the user can either choose that frequency or the frequency divided by 16 as the input to the prescaler of
each timer. Alternatively, the user may prefer TINn to be the clock source. TINn is internally synchronized
to the internal clock. If the user has chosen to internally cascade two 16-bit timers to a 32-bit timer, then a
timer can use the clock generated by the output of another timer.
The clock input source is selected by the corresponding GTMDRn[ICLK] bits. The prescalers
(GTMDRn[SPS] and GTPSRn[PPS]) can be programmed to divide the clock input by values from 1 to
65,537 and the output of the prescaler is used as an input to the 16-bit counters. The best resolution of the
timer is one clock cycle (3 ns at a 333-MHz system clock, for example). The maximum period (when the
reference value is all ones and the prescaler divides by 256) for one 16-bit timer is ~50 ms at 333 MHz.
5.7.6.2 Reference Modes
Each timer can be configured to count until a reference is reached and then either begin a new time count
immediately or continue to run. The FRR bit of the corresponding GTMRR selects each mode.
• Free run reference mode (GTMDRn[FRR] = 0)
The corresponding timer count continues to increment after the reference value is reached.
• Reset reference mode (GTMDRn[FRR] = 1)
The corresponding timer count is reset immediately after the reference value is reached.
Upon reaching the reference value, the corresponding GTEVRn[REF] bit is set and an interrupt is issued
if GTMDRn[ORI] = 1. The timers can output a signal on the timer output pin TOUTn if the reference value
is reached (selected by the corresponding GTMDRn[OM]). This signal can be an active-low pulse or a
toggle of the current output. The output can also be connected internally to the input of another timer,
resulting in a 32- or 64-bit timer.
5.7.6.3 Capture Modes
In addition, each timer has a 16-bit field in GTCPR, used to latch the value of the counter when a defined
transition of TINn is sensed by the corresponding input capture edge detector. The timers may be
gated/restarted by an external gate signals (TGATEn) that controls the timers. The type of transition
triggering the capture is selected by the corresponding GTMDRn[CE] bits. Upon a capture or reference
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-62 Freescale Semiconductor