Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 51

Figure
Number
15-109 TMR_CNT_H Register Definition ................................................................................... 15-117
15-110 TMR_ADD Register Definition........................................................................................ 15-118
15-111 TMR_ACC Register Definition ........................................................................................ 15-118
15-112 TMR_PRSC Register Definition ...................................................................................... 15-119
15-113 TMROFF_H/L Register Definition .................................................................................. 15-119
15-114 TMR_ALARM1-2_H/L Register Definition .................................................................... 15-120
15-115 TMR_FIPERn Register Definition ................................................................................... 15-121
15-116 TMR_ETTS1-2_H/L Register Definition ......................................................................... 15-121
15-117 Control Register Definition............................................................................................... 15-124
15-118 Status Register Definition ................................................................................................. 15-125
15-119 AN Advertisement Register Definition............................................................................. 15-126
15-120 AN Link Partner Base Page Ability Register Definition .................................................. 15-128
15-121 AN Expansion Register Definition ................................................................................... 15-129
15-122 AN Next Page Transmit Register Definition .................................................................... 15-130
15-123 AN Link Partner Ability Next Page Register Definition .................................................. 15-130
15-124 Extended Status Register Definition ................................................................................. 15-131
15-125 Jitter Diagnostics Register Definition ............................................................................... 15-132
15-126 TBI Control Register Definition ....................................................................................... 15-133
15-127 eTSEC-MII Connection .................................................................................................... 15-135
15-128 eTSEC-RMII Connection ................................................................................................. 15-136
15-129 eTSEC-RGMII Connection............................................................................................... 15-137
15-130 eTSEC-RTBI Connection ................................................................................................. 15-138
15-131 Definition of Custom Preamble Sequence ........................................................................ 15-149
15-132 Definition of Received Preamble Sequence...................................................................... 15-149
15-133 Ethernet Address Recognition Flowchart ......................................................................... 15-151
15-134 Sample C Code for Computing eTSEC Hash Table Indices............................................. 15-153
15-135 Location of Frame Control Blocks for TOE Parameters .................................................. 15-161
15-136 Transmit Frame Control Block ......................................................................................... 15-161
15-137 Receive Frame Control Block........................................................................................... 15-163
15-138 Structure of the Receive Queue Filer Table ...................................................................... 15-168
15-139 1588 Timer Design Partition ............................................................................................. 15-179
15-140 Ethernet Sampling Points for 1588 ................................................................................... 15-180
15-141 PTP Packet Format............................................................................................................ 15-181
15-142 Buffer Format for Transmit timestamp Insertion .............................................................. 15-183
15-143 Transmit Frame Control Block ......................................................................................... 15-183
15-144 Example of eTSEC Memory Structure for BDs ............................................................... 15-186
15-145 Buffer Descriptor Ring...................................................................................................... 15-186
15-146 Transmit Buffer Descriptor ............................................................................................... 15-187
15-147 Mapping of TxBDs to a C Data Structure......................................................................... 15-187
15-148 Receive Buffer Descriptor................................................................................................. 15-190
15-149 Mapping of RxBDs to a C Data Structure ........................................................................ 15-191
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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