Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 693

Inputs
Encrypt
(outbound)
Outputs
Inputs
Decrypt
(inbound)
Outputs Computed
The context for CCM encryption/MAC generation is:
• Reg 1–2, session specific 128-bit initialization vector (from memory)
• Reg 3–4, 128 bits of zero padding
• Reg 5–6, session specific counter (initial counter value) (from memory)
• Reg 7, counter modulus exponent (msb<--lsb). Should be fixed at 0x0000_0080.
Note that the counter modulus for CCM mode is currently defined as 2
value has been made programmable in the SEC in case the final version of 802.11i uses a different counter
modulus. Because this is a programmable field, it must be generated and stored along with other session
specific information for loading into the AESU context register prior to CCM encryption.
CCM encryption processing—With the session specific key and context, the AESU will perform the
following operations.
1. Initialize the IV, and encrypt with the symmetric key.
2. In CBC fashion, take the output of step 1, hash with the first block of plaintext, and encrypt with
the symmetric key.
3. Continue as in step 2 until the final block of plaintext has been processed. The result of the
encryption of the final block of plaintext with the symmetric key is the MAC tag. The full 128 bits
of MAC data is written to context registers 1–2, for use in the next phase of CCM processing.
Once the MAC tag has been generated (step 3), the MAC tag, along with the plaintext is encrypted with
the AESU operating in counter mode.
4. The first item to be encrypted in counter mode is the counter (initial counter value) from context
registers 5–6. The counter is encrypted with the symmetric key, and the result is hashed with the
MAC tag (retrieved from context registers 1–2) to produce the MIC (encrypted MAC), which is
then stored in context registers 3–4. At the completion of CCM encrypt processing, this MIC is
output to memory (per the descriptor pointer) for the host to append to the 802.11i frame. Note that
the MIC written out to memory by the AESU is the full 128 bits. The host must only append the
most-significant 64 bits to the frame as the MIC.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1 2
IV
MAC 0
IV
0
MAC
Figure 14-35. AESU CCM Context Registers
Context Registers
3 4
0
MIC 0
MIC 0
Decrypted 0
MAC
Security Engine (SEC) 2.2
5 6
Initial Counter
Initial Counter
128
making the exponent 128. This
7
Counter
Modulus
Exponent
Counter
Modulus
Exponent
14-51