Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 359

Chapter 8
Integrated Programmable Interrupt Controller (IPIC)
This chapter describes the integrated programmable interrupt controller (IPIC), including a definition of
the external signals and their functions. Also, the configuration, control, and status registers are described
in this chapter. Note that individual chapters in this reference manual describe specific initialization
aspects for each individual block.
8.1 Introduction
This chapter describes the IPIC interrupt protocol, various types of interrupt sources controlled by the IPIC
unit, and the IPIC registers with some programming guidelines. The programming model is similar to the
interrupt controller of the MPC8260. The interrupt controller provides interrupt management that is
responsible for receiving hardware-generated interrupts from different sources (both internal and
external). It also prioritizes and delivers the interrupts to the CPU for servicing. The IPIC prioritizes and
manages interrupts from the following controller units:
• DDR memory controller (DDR)
• Enhanced local bus memory controller (eLBC)
• PCI
• Four-channel DMA controller (DMA)
• Message unit (MU)
• Dual three-speed Ethernet controllers (eTSEC1 and eTSEC2)
• DUART communication module (DUART)
• USB 2.0 dual role controller (USB DR)
• Security engine (SEC)
• System bus arbiter (SBA)
• Periodic interval timer (PIT)
• Real time clock timer (RTC ALR and RTC SEC)
• Eight global timers (GTM1–GTM8)
• Software watchdog timer (WDT)
2
• I C controllers (I
• SPI controller (SPI)
• Power management controller (PMC)
• General-purpose I/O controller (GPIO)
• External pins (IRQ[0:4])
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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C1 and I C2)
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