Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 973

Bits Name
24–25 REFSEL[1:0]
26 OTG_PORT
27 KEEP_OTG_ON
28 LSF_EN
29 USB_EN
30 WU_INT_EN
31 ULPI_INT_EN
16.4 Functional Description
The USB DR module can be broken down into functional sub-blocks, which are described below.
16.4.1 System Interface
The system interface block contains all the control and status registers that allow a processor to interface
to the USB DR module. These registers allow the processor to control the configuration of the module,
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-37. CONTROL Field Descriptions (continued)
The REFSEL signals are used to set the frequency value for the UTMI PLL reference clock. These
bit fields are not relevant if not in UTMI mode.
00 Reserved
01 Reference clock frequency is 24 MHz. This is the default frequency.
10 Reference clock frequency is 48 MHz
11 Reserved
Enables the OTG comparators.
0 OTG comparators disabled
1 OTG comparators enabled
Keeps the OTG comparators on during low power suspend.
0 OTG comparators disabled during suspend
1 OTG comparators enabled during suspend
This bit is used to enable the UTMI line state filter. When enabled the UTMI linestate[1:0] output
of the UTMI PHY are filtered to account for any skew between the USB differential data lines
(DP/DM).
0 Line state filter disabled
1 Line state filter enabled
UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantlly different times to complete power-on reset.
1 Normal operation
0 Safe mode
This bit is used to mask/unmask the system wakeup interrupt signal
0 System wakeup interrupt disabled
1 System wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set for the system wakeup interrupt generation.
Used to enable the ULPI low power wakeup interrupt from the PHY when the PHY is in low power
mode only.
0 ULPI low power wakeup interrupt disabled
1 ULPI low power wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set
Description
Universal Serial Bus Interface
16-45