Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 799

Table 15-57 describes the fields of the TR127 register.
Bits Name
0–9 — Reserved
10–31 TR127 Transmit and receive 65- to 127-byte frame counter—Increments for each good or bad frame transmitted and
received which is 65–127 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
15.5.3.6.3 Transmit and Receive 128- to 255-Byte Frame Counter (TR255)
Figure 15-54 describes the definition for the TR255 register.
Offset eTSEC1:0x2_4688; eTSEC2:0x2_5688
0
R
W
Reset
Figure 15-54. Transmit and Received 128- to 255-Byte Frame Register Definition
Table 15-58 describes the fields of the TR255 register.
Bits Name
0–9 — Reserved
10–31 TR255 Transmit and receive 128- to 255-byte frame counter—Increments for each good or bad frame transmitted and
received which is 128–255 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
15.5.3.6.4 Transmit and Receive 256- to 511-Byte Frame Counter (TR511)
Figure 15-55 describes the definition for the TR511 register.
Offset eTSEC1:0x2_468C; eTSEC2:0x2_568C
0
R
W
Reset
Figure 15-55. Transmit and Received 256- to 511-Byte Frame Register Definition
Table 15-59 describes the fields of the TR511 register.
Bits Name
0–9 — Reserved
10–31 TR511 Increments for each good or bad frame transmitted and received which is 256–511 bytes in length, inclusive
(excluding preamble and SFD but including FCS bytes).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-57. TR127 Field Descriptions
9 10
—
Table 15-58. TR255 Field Descriptions
9 10
—
Table 15-59. TR511 Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
TR255
All zeros
Description
TR511
All zeros
Description
Access: Read/Write
31
Access: Read/Write
31
15-81