Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 215

Table 5-5 defines the bit fields of IMMRBAR.
'
Bits Name
0–11 BASE_ADDR
12–31 —
5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)
The alternate configuration base address register (ALTCBAR) is used to define the base address for an
alternate 1-Mbyte region of configuration space to be used by the boot sequencer. By loading the proper
boot sequencer command in the serial ROM, the base address in the ALTCBAR can be combined with the
20 bits of address offset supplied from the serial ROM to generate a 32-bit address. Thus, by configuring
this register, the boot sequencer has access to the entire memory map, one 1-Mbyte block at a time. See
Section 17.4.5, "Boot Sequencer Mode,"
ALTCBAR is not considered a local access window on its own, so the boot
sequencer must configure one of the other eight local access windows
properly to reach the desired target peripherals.
The alternate configuration base address register is shown in
Offset 0x08
0
R
BASE_ADDR
W
Reset
Figure 5-3. Alternate Configuration Base Address Register (ALTCBAR)
Table 5-6 defines the bit fields of ALTCBAR.
'
Bits Name
0–11 BASE_ADDR Identifies the12 most-significant address bits of an alternate base address used for boot sequencer
configuration accesses.
12–31 — Reserved. Write has no effect, read returns 0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-5. IMMRBAR Bit Settings
Identifies the 12 most-significant address bits of the base of the 1-Mbyte internal memory window.
Reserved. Software must write all zeros.
for more information.
11 12
Table 5-6. ALTCBAR Bit Settings
Description
NOTE
Figure 5-3.
All zeros
Description
System Configuration
Access: Read/Write
—
31
5-7