Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 471

must be set up before issuing a write command to the UPM, or before issuing a FCM operation sequence
that uses MDR to source address or data bytes.
Offset 0x0_5088
0
R
W
Reset
Offset 0x0_5088
0
R
AS3
W
Reset
Table 10-13 describes MDR[D].
Bits Name
0–31 D In UPM mode, D is the data to be read or written into the RAM array when a write or read command is
supplied to the UPM (M x MR[OP] = 01 or M x MR[OP] = 10).
0–7 AS3 In FCM mode, AS3 is the fourth byte of address sent by a custom address write operation, or the fourth byte
of data read from a read status operation.
8–15 AS2 In FCM mode, AS2 is the third byte of address sent by a custom address write operation, or the third byte of
data read from a read status operation.
16–23 AS1 In FCM mode, AS1 is the second byte of address sent by a custom address write operation, or the second
byte of data read from a read status operation.
24–31 AS0 In FCM mode, AS0 is the first byte of address sent by a custom address write operation, or the first byte of
data read from a read status operation.
10.3.1.7 Special Operation Initiation Register (LSOR)
The special operation initiation register (LSOR), shown in
special operation on the indicated bank. Writing to LSOR activates a special operation on bank
LSOR[BANK] provided that the bank is valid and controlled by a memory controller whose mode OP field
is set to a value other than 'normal operation.' If eLBC is currently busy with a memory transaction,
writing LSOR completes immediately, but the special operation request is queued until eLBC can service
it. To avoid race conditions between software and a busy eLBC, registers that affect currently running
special operation and LSOR must not be re-written before a pending special operation has been completed.
The UPM and FCM have different indications of when such special operations are completed. The
behavior of eLBC is unpredictable if special operation modes are altered between LSOR being written and
the relevant memory controller completing that access.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 10-9. UPM Data Register in UPM Mode (MDR)
7 8
AS2
Figure 10-10. FCM Data Register in FCM Mode (MDR)
Table 10-13. MDR Field Description
D
All zeros
15 16
AS1
All zeros
Description
Figure 10-11, is used by software to trigger a
Enhanced Local Bus Controller
Access: Read/Write
Access: Read/Write
23 24
AS0
10-23
31
31