Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 381

Table 8-21 lists the implemented SERSR bits. Note that these field assignments are valid for SERMR and
SERFR.
Table 8-22 defines the bit fields of SERSR.
Bits Name
0–31 INT n Each implemented bit in the SERSR, listed in
(mcp). When an error interrupt signal is received, the interrupt controller sets the corresponding SERSR bit.
SERSR bits are cleared by writing ones to them. Unmasked event register bits should be cleared before clearing
SERSR bits. Because the user can only clear bits in this register, writing zeros to this register has no effect.
SERSR bits are cleared by power-on reset. Subsequent soft and hard resets do not affect SERSR bit states.
For unimplemented bits (listed as reserved in
8.5.14 System Error Mask Register (SERMR)
Each implemented bit in SERMR, shown in
source (MCP). The user masks an MCP by clearing and enables an interrupt by setting the corresponding
SERMR bit. When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of
the corresponding SERMR bit although no MCP request is passed to the core in this case. The SERMR
can be read by the user at any time.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 8-21. SERSR/SERMR/SERFR Bit Assignments
Bits
0
1
2
3
4
5
6
7
8–14
15
16–31
1
This bit is valid only if the IRQ0 signal is
configured as an external MCP interrupt
(SEMSR[SIRQ0] = 1)
Table 8-22. SERSR Field Descriptions
Figure
Integrated Programmable Interrupt Controller (IPIC)
Field
1
IRQ0
WDT
SBA
—
—
PCI
—
MU
—
—
—
Description
Table 8-21, corresponds to an external and an internal error source
Table 8-21), writes are ignored, read = 0
8-17, corresponds to an external and an internal mcp
8-23