Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 292

System Configuration
D3
Cold
Power Down
VDDC,VDD
All
States
PMCCR1[NEXT_STATE]=01b
NOTES:
1) Wake-up case #1: Wake-up will occur as a result of one of the following: e300 interrupt or bus activity, PMCER[X] &
PMCMR[X] = 1, where X is one of {USB, TSEC, GPIO, PCI, interrupt, timer}, PMCCR1[NEXT_STATE] = 00. The device
will wake-up directly as host or agent. PCI_PME can be generated manually to host if desired.
2) Wake-up case #2: As host (PMCCR[PME_EN] = 0), Wake-up will occur as a result of one of the following: PMCER[X]
& PMCMR[X] = 1, where X is one of {USB, TSEC, GPIO, PCI, interrupt, timer}. As agent (PMCCR[PME_EN]=1) wake-up
event will cause PCI_PME to be asserted; the device will wake up when the host sets PCIPMR1[Power_State] = 00, which
causes PMCCR1[NEXT_STATE] = 00.
3) Before the transition to D3Warm, VDD power is switched off. VDDC remains constant.
4) Before the transition from D3Warm, VDD power is switched on.
5) D1, D2 & D3Hot modes are supported through use of the e300 Doze, Nap, and Sleep modes respectively. Transitions
from D1–D3Hot are triggered as follows: the e300 internal time base unit invokes a request to exit low power state or e300
receives an interrupt request, including interrupt from a defined wake-up event.
6) Transitions to D3Cold implies power-down of VDDC and VDD supplies.
7) Transitions from D3Warm go to the D0-non-initialized state, meaning a portion of the chip (e300, DDR etc.) will need
to be initialized. Portions of the chip which are not powered-off may not need to be initialized.
5.8.3.7.2 MPC8313E Low Power Sequencing
The following sections describe the sequence of events that occur when entering or exiting the device's
lowest power state (D3Warm). Host and agent cases are described separately.
PMC Power-Down When the MPC8313E is a PCI Agent
In this case the PCI device driver runs on an external PCI host. It interfaces to the device through PCI
configuration interface.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-84
PORESET
Not initialized
SW Initialization
PMCCR1[NEXT_STATE]=00b
D0
PMCCR1[NEXT_STATE]=10b
Active
&& PMCCR1[POWER_OFF]=0
PMCCR1[POWER_OFF]=1
PMCCR1[NEXT_STATE]=00b || int
|| bus activity)
Figure 5-57. Power State Transitions Supported
{PMCCR[eTSEC1]=1b ||
PMCCR[GPIO]=1b || PMCR[Timer]=1 ||
PMCR[Interrupt]=1b}
D0
PMCCR1[NEXT_STATE]=00b
PMCCR1[NEXT_STATE]=11b
D3
Warm
D1
D2
D3
Hot
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