Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 389

8.6.5 Highest Priority Interrupt
In addition to the group relative priority option, SICFR[HPI] can be used to specify one interrupt source
as having the highest priority. This interrupt remains within the same interrupt level as the other interrupt
controller interrupts, but is serviced before any other interrupt in
If the highest priority feature is not used, the IPIC selects the interrupt request in MIXA0 to be the highest
priority interrupt and the standard interrupt priority order is used from
updated dynamically to allow the user to change a normally low priority source into a high priority-source
for a period as needed.
8.6.6 Interrupt Source Priorities
Each of the IPIC's internal and external interrupt sources can independently assert one interrupt request to
the core. Table 8-31 shows the prioritization of these interrupt sources. As described in previous sections,
flexibility exists in the relative ordering of the interrupts, but, in general, relative priorities are as shown.
A single interrupt priority number is associated with each table entry.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 8-31. 7Interrupt Source Priority Levels
Priority Interrupt Source Description
1
2 MIXA0 (Grouped/Spread)
3
4
5
6
7–10
11
12–15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Integrated Programmable Interrupt Controller (IPIC)
Table 8-31.
Table
Highest
MIXA1 (Grouped)
MIXA2 (Grouped)
MIXA3 (Grouped)
MIXB0 (Spread)
Reserved
MIXA1 (Spread)
Reserved
MIXB0 (Grouped)
MIXB1 (Grouped)
MIXB2 (Grouped)
MIXB3 (Grouped)
MIXB1 (Spread)
SYSA0 (Grouped)
SYSA1 (Grouped)
SYSA2 (Grouped)
SYSA3 (Grouped)
MIXA2 (Spread)
SYSA4 (Grouped)
SYSA5 (Grouped)
SYSA6 (Grouped)
SYSA7 (Grouped)
8-31. SICFR[HPI] can be
8-31