Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 478

Enhanced Local Bus Controller
Table 10-19 describes LTEATR fields.
Bits Name
0–2 — Reserved
3 RWB Transaction type for the error:
0 The transaction for the error was a write transaction.
1 The transaction for the error was a read transaction.
4–10 — Reserved
11–15 SRCID Captures the source of the transaction when this information is provided on the internal interface to the eLBC.
16–19 PB Error on block for FCM. For FCM, there are at most four 512-byte page blocks (for a large page device)
checked by ECC. A bit is set for the 512-byte block that had an uncorrectable ECC error on read (bit 16
represents block 0, the first 512 bytes of a page; if ORx[PGS] = 0, bits 17–19 are always 0).
20–23 BNK Memory controller bank. There is one error status bit per memory controller bank (bit 20 represents bank 0).
A bit is set for the local bus memory controller bank that had an error.
24–30 — Reserved
31 V Error attribute capture is valid. Indicates that the captured error information is valid.
0 Captured error attributes and address are not valid.
1 Captured error attributes and address are valid.
10.3.1.13 Transfer Error Address Register (LTEAR)
The transfer error address register (LTEAR) captures the address of a transaction that caused an
error/event. The transfer error address register (LTEAR) is shown in
Offset 0x0_50C0
0
R
W
Reset
Table 10-20 describes LTEAR fields.
Bits Name
0–31 A Transaction address for the error. For GPCM and UPM, holds the 32-bit address of the transaction resulting
in an error. For FCM, this register is undefined.
10.3.1.14 Transfer Error ECC Register (LTECCR)
The transfer error ECC register (LTECCR) captures single bit and multibit errors per 512-byte sector in
FCM mode. LTECCR, shown in
not set bits. It captures the errors during full page read transfers on FCM command completion event,
provided ECC check is enabled in BRx[DECC].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-30
Table 10-19. LTEATR Field Descriptions
Figure 10-17. Transfer Error Address Register (LTEAR)
Table 10-20. LTEAR Field Descriptions
Figure 10-18, is a write-1-to-clear register. Write operations can clear but
Description
Figure
A
All zeros
Description
10-17.
Access: Read/Write
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