Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 393

Figure 8-26 shows an example of how the masking occurs, using a DDR block as an example.
DDR EVENT
Event
Bit
DDR MASK
Mask
Bit
8.6.8 Interrupt Vector Generation and Calculation
Pending unmasked interrupts are presented to the core in order of priority according to
interrupt vector that allows the core to locate the interrupt service routine is made available to the core by
interrupt handler software reading SIVCR. The interrupt controller passes an interrupt vector
corresponding to the highest-priority, unmasked, pending interrupt in response to a read of SIVCR.
Table 8-5 lists the encodings for the seven low-order bits of the interrupt vector.
8.6.9 Machine Check Interrupts
The PIC supports the non-maskable machine check interrupts. When an error interrupt signal is received,
the interrupt controller indicates the source by setting the corresponding SERSR bit. These sources are
listed in Table 8-21.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
SIPNR
XX Input (or
XX Event Bits)
SIMSR
Mask
Bit
Figure 8-26. DDR Interrupt Request Masking
Integrated Programmable Interrupt Controller (IPIC)
(Other Unmasked Requests)
Request to
the core
Table 8-31. The
8-35