Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 229

5.3.2.5 System I/O Configuration Register Low (SICRL)
The system I/O configuration register low (SICRL) controls the multiplexing of some of the device I/O
pins. Each bit or set of bits in the SICRL selects which function is used by a certain group of the device
pins.
Figure 5-14 shows SICRL.
Offset 0x00114
0
R
—
W
Reset 0
8
R
SPI_B
W
Reset 1
16
R
W
Reset
24
R
W
Reset
Table 5-28 defines the bit fields of SICRL. Each Pin Function column lists the name of the multi-function
pin used in this option. Some groups have only two options (shown as Pin Function 0 and Pin Function 1)
and therefore, only one control bit. In this case they can only have a value of 0b0 or 0b1. Other groups may
have four options (shown as Pin Function 0, Pin Function 1, Pin Function 2, and Pin Function 3) and
therefore, two control bits. In this case they can have a value of 0b00, 0b01, 0b10, or 0b11. Use the
notations '0bN' or '0bNN' according to whether a group has one or two control bits, respectively.
SICRL[Bits]
Value
Bits Group Pin Function 0
0–1 Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1 2
LBC
0 1
9 10
SPI_C
1 1
17 18
—
25 26
—
Figure 5-14. System I/O Configuration Register Low (SICRL)
Table 5-28. SICRL Bit Settings
0b0/0b00 0b1/0b01
Pin Function 1
—
3 4
UART
1 0
11 12
SPI_D
1 1
19 20
USB_DR
All zeros
27 28
ETSEC1_A
Depends on RCW
0b10
Pin Function 2
— —
System Configuration
Access: Read/Write
5 6
SPI_A
0 1
13 14
—
1 0
21 22
—
29 30
ETSEC2_A
0b11
Pin Function 3
—
7
1
15
0
23
31
Reset
Value
00
5-21