Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 956

Universal Serial Bus Interface
Bits Name
20 WLCN Wake on connect enable. Writing this bit to a one enables the port to be sensitive to device connects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
19–16 PTC Port test control. Any other value than zero indicates that the port is operating in test mode.
0000 Not Enabled
0001 J_STATE
0010 K_STATE
0011 SEQ_NAK
0100 Packet
0101 FORCE_ENABLE
0110–1111 Reserved, should be cleared
Refer to Chapter 7 of the USB Specification Revision 2.0 [3] for details on each test mode.
15–14 PIC Port indicator control. Control the link indicator signals. These signals are valid for host mode only.
00 Off
01 Amber
10 Green
11 Undefined
Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used.
This field is output from the module on the USB port control signals for use by an external LED driving circuit.
13 PO Port owner. Unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. System software uses this
field to release ownership of the port to a selected the module (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A
one in this bit means that an internal companion controller owns and controls the port.
Port owner hand-off is not implemented in this design, therefore this bit is always 0.
12 PP Port power. Represents the current setting of the switch (0=off, 1=on). When power is not available on a port
(that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port, the PP bit in each affected port is transitioned
by the host controller driver from a one to a zero (removing power from the port).
This feature is implemented in the host/OTG controller (PPC = 1).
In a device-only implementation port power control is not necessary, thus PPC and PP = 0.
11–10 LS Line status. Reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use of line
status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS is
managed by hardware.
00 SE0
10 J-state
01 K-state
11 Undefined
9 — Reserved, should be cleared
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-28
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
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