Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 797

Table 15-52 describes the fields of a MACnADDR1 register.
Bit
0–7 Exact Match Address, 6th Octet Holds the sixth octet of the exact match address. The sixth octet
8–15 Exact Match Address, 5th Octet Holds the fifth octet of the exact match address. The fifth octet
16–23 Exact Match Address, 4th Octet Holds the fourth octet of the exact match address. The fourth octet
24–31 Exact Match Address, 3rd Octet Holds the third octet of the exact match address. The third octet
15.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers
(MAC01ADDR2–MAC15ADDR2)
The MAC01ADDR2–MAC15ADDR2 registers are written by the user with the unicast or multicast
addresses aliasing the MAC.
registers.
Offset eTSEC1:0x2_454C+8× n ; eTSEC2:0x2_554C+8× n
0
R
Exact Match Address,
2nd Octet
W
Reset
Figure 15-51. MAC Exact Match Address x Part 2 Register Definition
Table 15-53 describes the fields of a MACxADDR2 register.
Bit
0–7 Exact Match Address, 2nd Octet
8–15 Exact Match Address, 1st Octet
16–31
15.5.3.6 MIB Registers
This section describes the MIB registers. The eTSEC RMON module has 37 separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-54. MAC n ADDR1 Field Descriptions
Name
(destination address bits 40
(destination address bits 32
(destination address bits 24
(destination address bits 16
Figure 15-51 describes the definition for all of the fifteen MACxADDR2
7 8
Exact Match Address,
1st Octet
Table 15-55. MAC01ADDR2–MAC15ADDR2 Field Descriptions
Name
This field holds the second octet of the exact match address. The
second octet (destination address bits 8–15) defaults to a value of
0x0.
This field holds the first octet of the exact match address. The first
octet (destination address bits 0–7) defaults to a value of 0x0.
— Reserved
Enhanced Three-Speed Ethernet Controllers
Description
–
47) defaults to a value of 0x0.
–
39) defaults to a value of 0x0.
–
31) defaults to a value of 0x0.
–
23) defaults to a value of 0x0.
15 16
All zeros
Description
Access: Read/Write
—
15-79
31