Page 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual Supports MPC8313E MPC8313 MPC8313ERM Rev. 3 08/2010...
Page 2 Freescale Semiconductor Japan Ltd. or for any other application in which the failure of the Freescale Semiconductor product Headquarters could create a situation where personal injury or death may occur. Should Buyer...
Page 3: Table Of Contents
High-End Printer I/O Processor................. 1-20 1.3.3 IEEE Std. 1588 in Test and Measurement and Industrial Automation ...... 1-21 1.3.4 IEEE Std. 802.11n WLAN Access Point ..............1-23 1.3.5 Media Server......................1-24 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 4 Reset Configuration Word High Register (RCWHR)..........4-15 4.3.2.2.1 PCI Host/Agent Configuration ................4-16 4.3.2.2.2 Boot Memory Space (BMS) ................4-17 4.3.2.2.3 Boot Sequencer Configuration ................4-17 4.3.2.2.4 Boot ROM Location ..................4-18 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 5 Output Clock Control Register (OCCR)..............4-38 4.5.2.3 System Clock Control Register (SCCR)..............4-39 Chapter 5 System Configuration Introduction........................5-1 Local Memory Map Overview and Example ..............5-1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 6 System General Purpose Register High (SGPRH) ..........5-17 5.3.2.3 System Part and Revision ID Register (SPRIDR) ..........5-18 5.3.2.3.1 SPRIDR[PARTID] Coding................5-18 5.3.2.4 System Priority and Configuration Register (SPCR) ..........5-18 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 7 Periodic Interval Timer (PIT) ..................5-43 5.6.1 PIT Overview......................5-44 5.6.2 PIT Features....................... 5-44 5.6.3 PIT Modes of Operation .................... 5-44 5.6.4 PIT External Signal Description ................5-45 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 8 PMC Memory Map/Register Definition ..............5-67 5.8.2.1 Power Management Controller Configuration Register (PMCCR)....... 5-68 5.8.2.2 Power Management Controller Event Register (PMCER)........5-68 5.8.2.3 Power Management Controller Mask Register (PMCMR) ........5-70 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 viii Freescale Semiconductor...
Page 9 Arbitration Policy ...................... 6-12 6.3.1.1 Address Bus Arbitration with PRIORITY[0:1] ............. 6-12 6.3.1.2 Address Bus Arbitration with REPEAT ..............6-13 6.3.1.3 Address Bus Arbitration After ARTRY..............6-14 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 10 7.1.7.4 Clock Multiplier....................7-12 7.1.7.5 Core Performance Monitor ..................7-12 PowerPC Architecture Implementation ................. 7-13 Implementation-Specific Information................7-13 7.3.1 Register Model......................7-14 7.3.1.1 UISA Registers ...................... 7-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 11 IPIPC Modes of Operation ....................8-4 8.3.1 Core Enable Mode ....................... 8-4 8.3.2 Core Disable Mode ...................... 8-5 IPIC External Signal Description ..................8-5 8.4.1 IPIC External Signals Overview.................. 8-5 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 12 Machine Check Interrupts..................8-35 Chapter 9 DDR Memory Controller Introduction........................9-1 Features ..........................9-2 9.2.1 Modes of Operation ..................... 9-3 External Signal Descriptions ................... 9-3 9.3.1 Signals Overview......................9-3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 13 DDR Data Beat Ordering................... 9-50 9.5.10 Page Mode and Logical Bank Retention ..............9-51 Initialization/Application Information ................9-52 9.6.1 Programming Differences between Memory Types ..........9-53 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xiii...
Page 14 Flash Block Address Register (FBAR)..............10-37 10.3.1.21 Flash Page Address Register (FPAR) ..............10-37 10.3.1.22 Flash Byte Count Register (FBCR) ..............10-39 10.3.1.23 Flash ECC Blockn Register (FECC0–FECC3) ........... 10-39 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 15 FCM Bank 0 Reset Initialization ..............10-72 10.4.3.4.2 Boot Block Loading into the FCM Buffer RAM..........10-72 10.4.4 User-Programmable Machines (UPMs)..............10-74 10.4.4.1 UPM Requests ..................... 10-75 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 16 10.5.4.6 NAND Flash Program Command Sequence Example ........10-99 10.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ..........10-100 10.5.6 Interfacing to ZBT SRAM Using UPM..............10-105 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 17 DMA Mode Register (DMAMRn) ................ 12-9 12.3.8.2 DMA Status Register (DMASRn) ............... 12-11 12.3.8.3 DMA Current Descriptor Address Register (DMACDARn) ......12-12 12.3.8.4 DMA Source Address Register (DMASARn)............. 12-13 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xvii...
Page 18 PCI Error Address Capture Register (PCI_EACR) ..........13-19 13.3.2.6 PCI Error Extended Address Capture Register (PCI_EEACR) ......13-20 13.3.2.7 PCI Error Data Low Capture Register (PCI_EDLCR)........13-20 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xviii Freescale Semiconductor...
Page 19 PCI Power Management Register 1 (PCIPMR1) ..........13-42 13.4 Functional Description....................13-43 13.4.1 PCI Bus Arbitration ....................13-43 13.4.1.1 Bus Parking......................13-44 13.4.1.2 Arbitration Algorithm..................13-44 13.4.1.3 Broken Master Lock-Out ..................13-45 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 20 Data Encryption Standard Execution Unit (DEU)..........14-5 14.1.2.2 Advanced Encryption Standard Execution Unit (AESU)........14-5 14.1.2.3 Message Digest Execution Unit (MDEU) ............. 14-5 14.1.3 Channel ........................14-6 14.1.4 SEC Controller......................14-7 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 21 14.4.2.13 MDEU FIFOs ...................... 14-40 14.4.3 Advanced Encryption Standard Execution Unit (AESU)........14-40 14.4.3.1 AESU Mode Register (AESUMR)..............14-40 14.4.3.2 AESU Key Size Register (AESUKSR) ............... 14-42 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 22 14.6.4.5 Identification Register (ID).................. 14-73 14.6.4.6 IP Block Revision Register.................. 14-73 14.6.4.7 Master Control Register (MCR) ................14-74 14.6.5 Snooping by Caches....................14-74 14.6.6 Interrupts........................14-75 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxii Freescale Semiconductor...
Page 23 Receive Control and Status Registers ............. 15-49 15.5.3.3.1 Receive Control Register (RCTRL) ..............15-49 15.5.3.3.2 Receive Status Register (RSTAT)..............15-51 15.5.3.3.3 Receive Interrupt Coalescing Register (RXIC) ..........15-53 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxiii...
Page 24 Transmit and Receive 128- to 255-Byte Frame Counter (TR255) ....15-81 15.5.3.6.4 Transmit and Receive 256- to 511-Byte Frame Counter (TR511) ....15-82 15.5.3.6.5 Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ....15-82 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxiv Freescale Semiconductor...
Page 25 15.5.3.6.42 Transmit Undersize Frame Counter (TUND)..........15-100 15.5.3.6.43 Transmit Fragment Counter (TFRG)............. 15-101 15.5.3.6.44 Carry Register 1 (CAR1) ................15-101 15.5.3.6.45 Carry Register 2 (CAR2) ................15-103 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 26 Status Register (SR)..................15-126 15.5.4.3.3 AN Advertisement Register (ANA) .............. 15-127 15.5.4.3.4 AN Link Partner Base Page Ability Register (ANLPBPA)......15-129 15.5.4.3.5 AN Expansion Register (ANEX) ..............15-130 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxvi Freescale Semiconductor...
Page 27 Frame Control Blocks..................15-161 15.6.3.2 Transmit Path Off-Load and Tx PTP Packet Parsing ........15-162 15.6.3.3 Receive Path Off-Load ..................15-163 15.6.4 Quality of Service (QoS) Provision ............... 15-165 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxvii...
Page 28 MII Interface Mode.................... 15-194 15.7.1.2 RGMII Interface Mode ..................15-197 15.7.1.3 RMII Interface Mode..................15-201 15.7.1.4 RTBI Interface Mode..................15-205 15.7.1.5 SGMII Interface Support ................... 15-208 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxviii Freescale Semiconductor...
Page 29 16.3.2.18 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI......16-36 16.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI ........16-36 16.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI ......... 16-37 16.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI..... 16-38 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxix...
Page 30 FSTN Back Path Link Pointer ................16-68 16.6 Host Operations ......................16-68 16.6.1 Host Controller Initialization ................... 16-69 16.6.2 Power Port........................ 16-70 16.6.3 Reporting Over-Current ................... 16-70 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 31 Split Transaction Execution State Machine for Isochronous......16-112 16.6.12.3.4 Periodic Isochronous—Do-Start-Split............16-113 16.6.12.3.5 Periodic Isochronous—Do Complete Split ........... 16-115 16.6.12.3.6 Complete-Split for Scheduling Boundary Cases 2a, 2b ........ 16-118 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxxi...
Page 32 Priming Receive Endpoints ................16-139 16.8.3.4 Interrupt/Bulk Endpoint Operational Model ............. 16-140 16.8.3.4.1 Interrupt/Bulk Endpoint Bus Response Matrix ..........16-141 16.8.3.5 Control Endpoint Operation Model ..............16-142 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxxii Freescale Semiconductor...
Page 33 SOF Interrupt ......................16-157 16.9.5 Embedded Design ....................16-157 16.9.5.1 Frame Adjust Register ..................16-157 16.9.6 Miscellaneous Variations from EHCI ..............16-157 16.9.6.1 Discovery......................16-157 16.9.6.1.1 Port Reset....................... 16-157 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxxiii...
Page 34 Filtering of SCLn and SDAn Lines ..............17-15 17.4.4.3 Clock Stretching ....................17-15 17.4.5 Boot Sequencer Mode....................17-15 17.4.5.1 Using the Boot Sequencer for Reset Configuration ..........17-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxxiv Freescale Semiconductor...
Page 35 MODEM Status Registers (UMSR1 and UMSR2) ..........18-16 18.3.1.12 Scratch Registers (USCR1 and USCR2) ............. 18-16 18.3.1.13 DMA Status Registers (UDSR1 and UDSR2)............. 18-17 18.4 Functional Description....................18-18 18.4.1 Serial Interface......................18-19 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxxv...
Page 36 SPI Receive Data Hold Register (SPIRD)............19-15 19.4.1.6.1 Reverse Mode SPMODE[REV] Examples ............. 19-15 19.5 Initialization/Application Information ................. 19-16 19.5.1 SPI Master Programming Example ................. 19-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxxvi Freescale Semiconductor...
Page 37 Changes From Revision 2 to Revision 3 ................ A-1 Changes From Revision 1 to Revision 2 ..............A-39 Changes From Revision 0 to Revision 1 ..............A-66 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xxxvii...
Page 38 Contents Paragraph Page Number Title Number MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xxxviii Freescale Semiconductor...
Page 39 Integrated Security Engine Functional Blocks..............1-10 USB Controllers Port Configuration..................1-13 MPC8313E Serving as the Main CPU in a Low-End Printer Application ......1-19 MPC8313E I/O Processor Implementation in a High-End Printer Application ....1-20 IEEE Std. 1588 in Test and Measurement ................1-21 IEEE Std.
Page 40 Timers Non-Cascaded Mode Block Diagram ............... 5-64 5-49 Timer Pair-Cascaded Mode Block Diagram ................. 5-65 5-50 Timers Super-Cascaded Mode Block Diagram..............5-65 5-51 Power Management Controller Configuration Register ............5-68 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 41 System External Interrupt Mask Register (SEMSR) ............8-20 8-15 System External Interrupt Control Register (SECNR) ............8-21 8-16 System Error Status Register (SERSR)................. 8-22 8-17 System Error Mask Register (SERMR) ................8-24 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 42 Write Timing Adjustments Example for Write Latency = 1 ..........9-47 9-30 DDR SDRAM Bank Staggered Auto Refresh Timing............9-48 9-31 DDR SDRAM Power-Down Mode ..................9-49 9-32 DDR SDRAM Self-Refresh Entry Timing ................9-50 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xlii Freescale Semiconductor...
Page 43 GPCM Relaxed Timing Back-to-Back Reads (XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)10-53 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 44 10-65 LCSn Signal Selection ......................10-85 10-66 LBS Signal Selection ......................10-86 10-67 UPM Read Access Data Sampling..................10-89 10-68 Effect of LUPWAIT Signal ....................10-90 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xliv Freescale Semiconductor...
Page 45 DMA Controller Block Diagram ..................12-16 12-19 DMA Chain of Segment Descriptors .................. 12-19 13-1 PCI Controller Block Diagram ..................... 13-2 13-2 PCI Interface External Signals....................13-5 13-3 PCI_CONFIG_ADDRESS Register ................... 13-13 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 46 Maximum Latency Configuration Register ................ 13-38 13-42 PCI Function Configuration Register ................. 13-38 13-43 PCI Arbiter Control Register (PCIACR) ................13-39 13-44 Hot Swap Register Block ....................13-40 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xlvi Freescale Semiconductor...
Page 47 14-23 MDEU ICV Size Register....................14-38 14-24 MDEU End-of-Message Register (MDEUEMR) ............... 14-38 14-25 MDEU Context Registers ....................14-39 14-26 AESU Mode Register (AESUMR) ..................14-40 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xlvii...
Page 48 TR03WT Register Definition....................15-45 15-17 TR47WT Register Definition....................15-45 15-18 TBDBPH Register Definition ..................... 15-46 15-19 TBPTR0–TBPTR7 Register Definition ................15-47 15-20 TBASE Register Definition ....................15-47 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 xlviii Freescale Semiconductor...
Page 49 Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ....15-83 15-60 Receive Byte Counter Register Definition................15-84 15-61 Receive Packet Counter Register Definition ..............15-84 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor xlix...
Page 50 Carry Mask Register 2 (CAM2) Register Definition............15-105 15-100 Receive Filer Rejected Packet Counter Register Definition ..........15-106 15-101 IGADDRn Register Definition ..................15-107 15-102 GADDRn Register Definition................... 15-108 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 51 Receive Frame Control Block................... 15-163 15-141 Structure of the Receive Queue Filer Table ..............15-168 15-142 1588 Timer Design Partition ..................... 15-181 15-143 Ethernet Sampling Points for 1588 ................... 15-181 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 52 Endpoint Control 1 to 5 (ENDPTCTRLn) ................16-40 16-30 Snoop 1 and Snoop 2 (SNOOPn)..................16-41 16-31 Age Count Threshold (AGE_CNT_THRESH)..............16-43 16-32 Priority Control (PRI_CTRL) ..................... 16-44 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 53 ULPI Data Transmit (PID)....................16-161 16-70 ULPI Data Receive ......................16-161 16-71 ULPI Register Write......................16-162 16-72 ULPI Register Read ......................16-162 17-1 C Block Diagram........................ 17-1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor liii...
Page 54 Example SPMODE[REV] = 1 SPMODE[LEN] = 7 MSB Sent First......... 19-15 19-14 Example SPMODE[REV] = 1 SPMODE[LEN] = 15 MSB Sent First....... 19-16 19-15 Example SPMODE[REV] = 0 SPMODE[LEN] = 15 LSB Sent First........ 19-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 55 GPIO Data Register (GPDAT) ....................21-4 21-5 GPIO Interrupt Event Register (GPIER) ................21-4 21-6 GPIO Interrupt Mask Register (GPIMR)................21-5 21-7 GPIO Interrupt Control Register (GPICR) ................21-5 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 56 Figures Figure Page Number Title Number MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 57 4-26 Configurable Clock Units ..................... 4-31 4-27 Reset Configuration and Status Registers Memory Map............4-32 4-28 RSR Field Descriptions......................4-34 4-29 RMR Field Descriptions ....................... 4-35 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lvii...
Page 58 DDRCDR Field Descriptions....................5-27 5-31 DDRDSR Field Descriptions ....................5-28 5-32 WDT Register Address Map....................5-30 5-33 SWCRR Bit Settings ......................5-31 5-34 SWCNR Bit Settings......................5-32 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lviii Freescale Semiconductor...
Page 59 PCI Bus Power Management State Support................5-76 5-73 Software-Controller Power-Down States—Basic Description ..........5-77 5-74 MPC8313E Agent Mode Wake-Up Support................. 5-81 5-75 MPC8313E Host Mode Wake-Up Support ................5-83 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 60 SMPRR_A Field Descriptions ....................8-19 8-18 SMPRR_B Field Descriptions ....................8-20 8-19 SEMSR Field Descriptions ....................8-21 8-20 SECNR Field Descriptions ....................8-22 8-21 SERSR/SERMR/SERFR Bit Assignments ................8-23 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 61 DDR1 Address Multiplexing ....................9-36 9-28 DDR2 Address Multiplexing ....................9-37 9-29 Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between Two Banks........................9-37 9-30 DDR SDRAM Command Table.................... 9-39 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 62 FCM Command, Address, and Write Data Timing Parameters.......... 10-67 10-35 FCM Read Data Timing Parameters ................... 10-70 10-36 Boot Bank Field Values after Reset for FCM as Boot Controller ........10-71 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxii Freescale Semiconductor...
Page 63 PCI Interface Signals—Detailed Signal Descriptions ............13-5 13-4 PCI Configuration Access Registers................... 13-11 13-5 PCI Memory-Mapped Registers ..................13-12 13-6 PCI_CONFIG_ADDRESS Field Descriptions ..............13-13 13-7 PCI_CONFIG_DATA Field Descriptions................13-15 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxiii...
Page 64 PCIPMR0 Field Descriptions....................13-41 13-44 PCIPMR1 Field Descriptions....................13-42 13-45 PCI Command Definitions....................13-46 13-46 Special Cycle Commands ....................13-56 14-1 Example Descriptor....................... 14-4 14-2 SEC Address Map......................... 14-8 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxiv Freescale Semiconductor...
Page 65 14-40 MCR Field Descriptions ..................... 14-74 15-1 eTSECn Network Interface Signal Properties ..............15-6 15-2 eTSEC Signals—Detailed Signal Descriptions ..............15-8 15-3 Module Memory Map Summary..................15-11 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 66 MACCFG2 Field Descriptions ................... 15-69 15-41 IPGIFG Field Descriptions ....................15-70 15-42 HAFDUP Field Descriptions ....................15-71 15-43 MAXFRM Descriptions...................... 15-72 15-44 MIIMCFG Field Descriptions..................... 15-73 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxvi Freescale Semiconductor...
Page 67 TMCA Field Descriptions....................15-93 15-82 TBCA Field Descriptions....................15-93 15-83 TXPF Field Descriptions ....................15-94 15-84 TDFR Field Descriptions ....................15-94 15-85 TEDF Field Descriptions ....................15-95 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxvii...
Page 68 15-123 TMR_FIPER Register Field Descriptions ................ 15-122 15-124 TMR_ETTS1-2_H Register Field Descriptions ............... 15-122 15-125 TBI MII Register Set......................15-124 15-126 CR Field Descriptions ....................... 15-125 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxviii Freescale Semiconductor...
Page 69 Shared RGMII Signals ...................... 15-190 15-165 RGMII Mode Register Initialization Steps ............... 15-190 15-166 RMII Interface Mode Signal Configuration..............15-193 15-167 Shared RMII Signals ......................15-193 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxix...
Page 70 16-33 SNOOPn Register Field Descriptions................. 16-41 16-34 AGE_CNT_THRESH Register Field Descriptions ............16-42 16-35 PRI_CTRL Register Field Descriptions ................16-43 16-36 SI_CTRL Register Field Descriptions ................16-43 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 71 Summary of Transaction Errors ..................16-120 16-74 Summary Behavior on Host System Errors ..............16-123 16-75 Endpoint Capabilities/Characteristics ................16-125 16-76 Current dTD Pointer......................16-126 16-77 Multiple Mode Control ..................... 16-127 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxxi...
Page 72 UDLB Field Descriptions ..................... 18-7 18-8 Baud Rate Examples ......................18-7 18-9 UIER Field Descriptions ....................... 18-9 18-10 UIIR Field Descriptions ...................... 18-10 18-11 UIIR IID Bits Summary ...................... 18-10 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxxii Freescale Semiconductor...
Page 73 GPODR Bit Settings ......................21-3 21-5 GPnDAT Bit Settings ......................21-4 21-6 GPIER Bit Settings ....................... 21-4 21-7 GPIMR Bit Settings ......................21-5 21-8 GPICR Bit Settings ....................... 21-5 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxxiii...
Page 74: Number Title Number
Tables Table Page Number Title Number MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxxiv Freescale Semiconductor...
Page 75: About This Book
About This Book This reference manual defines the functionality of the MPC8313E. It is written from the perspective of the MPC8313E, which is the superset device, and unless otherwise noted, the information applies also to the MPC8313. Note that the MPC8313 does not support a security engine.
Page 76 MPC8313E. It is optimized to process all the algorithms associated with IPSec. The SEC 2.2 (implemented in the MPC8313E) is derived from integrated security cores found in other members of the PowerQUICC family, including SEC 1.0,...
Page 77: General Information
Chapter 21, “General Purpose I/O (GPIO),” describes the general purpose I/O (GPIO) module in the MPC8313E device, including a definition of the external signals and functions they serve. Additionally, interrupt capabilities, pin description, and register settings are described. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
Page 78: Related Documentation
In some contexts, such as signal encodings, an unitalicized x indicates a don’t care An italicized x indicates an alphanumeric variable An italicized n indicates a numeric variable ¬ NOT logical operator MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxxviii Freescale Semiconductor...
Page 79: Acronyms And Abbreviated Terms
ARC four execution unit Buffer descriptor BIST Built-in self test Collision detect Collision Communication processor module Cyclic redundancy check Carrier sense Coherent system bus CSMA Carrier-sense multiple access MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxxix...
Page 80 Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group LALE LBC external address latch enable Local bus controller Least recently used Least-significant byte Least-significant bit Load/store unit MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxxx Freescale Semiconductor...
Page 81 RTBI Reduced ten-bit interface Real time clock module Receive RxBD Receive buffer descriptor Serial clock Serial data Start frame delimiter SGMII Serial gigabit media independent interface MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor lxxxi...
Page 82 Universal asynchronous receiver/transmitter ULPI USB low-pin count interface User-programmable machine Universal serial bus UTMI USB transceiver macrocell interface Unshielded twisted pair Watchdog timer Zero bus turnaround MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 lxxxii Freescale Semiconductor...
Page 83: Mpc8313E Powerquicc Ii Pro Processor Overview
This manual is written from the perspective of the MPC8313E, and unless otherwise noted, the information applies also to the MPC8313. Note that the MPC8313 does not support a security engine. The MPC8313E contains an ®...
Page 84 — Advanced encryption standard unit (AESU) – Implements the Rijndael symmetric-key cipher – Key lengths of 128-, 192-, and 256-bits – ECB, CBC, CCM, and counter (CTR) modes MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 85 — Support for two full-duplex FIFO interface modes — Multiple PHY interface configurations — Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 86 — MII management interface for control and status • Two SGMII PHY interfaces — Both interfaces share a single PLL — Each interface supports a 4-wire differential (Tx, Rx) interface — Support for auto-negotiation MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 87 — 16- and 8-bit ports — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 88 — On-chip split power supply controlled through external power switch for minimum standby power — Supports PME generation in PCI agent mode and PME detection in PCI host mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 89: Mpc8313E Architecture Overview
The core is a superscalar processor that can issue three instructions (two plus a branch) and completes and retires as many as two instructions per clock cycle. Instructions can execute out of order for increased performance; however, the core makes completion appear sequential. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 90 BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 91 JTAG/COP Clock Multiplier Interface Touch Load Buffer Processor Logic Copy-Back Buffer Bus Interface 32-Bit Address Bus 64-Bit Data Bus Figure 1-2. MPC8313E Integrated e300c3 Core Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 92: Security Engine
The DDR memory controller includes the following features: • Support for DDR1 and DDR2 SDRAM • 16- or 32-bit SDRAM data bus • Programmable settings for meeting all SDRAM timing parameters MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 1-10 Freescale Semiconductor...
Page 93: Dual Enhanced Three-Speed Ethernet Controllers
1.2.4 Dual Enhanced Three-Speed Ethernet Controllers The MPC8313E has two on-chip enhanced three-speed Ethernet controllers. The eTSECs incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/IEEE Std. 802.3 networks with MII, RMII, RGMII, RTBI, and SGMII physical interfaces. The eTSECs include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.
Page 94: Supported Etsec1 And Etsec2 Configurations
When in host mode, the PCI controller supports external signal isolation, thus enabling power shut off to external devices • Supports PCI Power Management 1.2 • Supports PME generation (agent) and Wake on PME MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 1-12 Freescale Semiconductor...
Page 95: Pci Bus Arbitration Unit
The host and device functions are both configured to support the following four types of USB transfers: • Bulk • Control • Interrupt • Isochronous TX Buffer Dual-Role Module (DR) RX Buffer DR Mux On-Chip PHY Figure 1-4. USB Controllers Port Configuration MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 1-13...
Page 96: Usb Dual-Role Controller
— Data buffer controls activated on a per-bank basis — Up to 256-byte bursts, arbitrarily aligned — Automatic segmentation of large transactions into memory accesses optimized for bus width and addressing capability MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 1-14 Freescale Semiconductor...
Page 97 — Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, and 256-Mbyte page banks • Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus error reporting) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 1-15...
Page 98: Integrated Programmable Interrupt Controller (Ipic)
Calling address identification interrupt • Bus busy detection • Software-programmable clock frequency • Software-selectable acknowledge bit • On-chip filtering for spikes on the bus • Address broadcasting supported MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 1-16 Freescale Semiconductor...
Page 99: Dma Controller
Clear to send (CTS) and ready to send (RTS) MODEM control functions • Software-selectable serial-interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate) • Line status registers • Line-break detection and generation MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 1-17...
Page 100: Serial Peripheral Interface (Spi)
32-bit timers, or one cascaded 64-bit counter Application Examples The internal features of the MPC8313E make it suitable for a wide variety of printer and network communication applications as described in this section. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3...
Page 101: Low-End Printer Cpu And Interface Asic
Required networking interfaces including USB, PCI, and Gigabit Ethernet are integrated on the MPC8313E, allowing for the CPU and interface ASIC to be consolidated in one device. As a result, an MFP application can be developed by combining the MPC8313E with the main ASIC (graphic processing ASIC) at a lower cost without the need to have separate a CPU and interface ASIC.
Page 102: High-End Printer I/O Processor
In order to reduce the power consumption in stand-by mode, the MPC8313E as a secondary I/O processor shuts off the power to the main CPU and maintains the system at very low power. Once the I/O processor detects data transfer through the LAN, USB and PCI or an interrupt from the push of a button on the panel, it quickly boots up the main CPU.
Page 103: Ieee Std. 1588 In Test And Measurement And Industrial Automation
The trigger inputs and outputs enable coordination of other devices. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 1-21...
Page 104 Industrial control applications typically augment IEEE Std. 1588 hardware to provide trigger inputs and outputs In summary, IEEE Std. 1588 support in the MPC8313E enables accurate synchronization of clocks with varying precision, resolution, and oscillator stability in distributed systems. IEEE Std. 1588 synchronizes individual clocks to maintain accurate distribution-wide timing.
Page 105: Ieee Std. 802.11N Wlan Access Point
Overview 1.3.4 IEEE Std. 802.11n WLAN Access Point Figure 1-9 illustrates the MPC8313E acting as an IEEE Std. 802.11n® WLAN access point. eTSEC 2x RGMII, 2x RTBI, 2x MII, 2x RMII 802.11 802.11 MPC8313E MAC/PHY or 2x SGMII eTSEC Figure 1-9. MPC8313E as a WLAN Access Point Current systems are being designed for IEEE Std.
Page 106: Media Server
Overview 1.3.5 Media Server Figure 1-10 shows how the MPC8313E can be configured as a media server. LAN Connection Hard Drive Flash Memory Ethernet IDE/SATA DDR2 Security 802.11 Wireless MPC8313E Or Bluetooth, UWB Audio MPEG Decode Audio (SPDIF) Decode LEDs...
Page 107: Internal Memory Mapped Registers
Chapter 2 Memory Map This chapter describes the MPC8313E memory map. The internal memory mapped registers are described, including a complete listing of all memory mapped registers with cross references to the sections detailing descriptions of each. Internal Memory Mapped Registers All of the memory mapped registers in the device are contained within a 1-Mbyte address region.
Page 108: Immr Memory Map
0x0_3100–0x0_31FF C2 controller 24 bytes 256 bytes 0x0_3200–0x0_32FF Reserved — 256 bytes 0x0_3300–0x0_33FF Reserved — 256 bytes 0x0_3400–0x0_37FF Reserved — 1 Kbyte 0x0_3800–0x0_3BFF Reserved — 1 Kbyte MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 109 0x2_0000–0x2_1FFF Reserved — 8 Kbytes 0x2_2000–0x2_2FFF Reserved — 4 Kbytes 0x2_3000–0x2_3FFF USB_DR module 1 Kbyte 4 Kbytes 0x2_4000–0x2_4FFF eTSEC 1 3 Kbytes + 1K reserved 4 Kbytes MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 110: Memory Map
LBLAWAR0—LBC local access window 0 attribute register 0x0000_0000 5.2.4.4/5-9 0x0_0028 LBLAWBAR1—LBC local access window 1 base address 0x0000_0000 5.2.4.3/5-8 register 0x0_002C LBLAWAR1—LBC local access window 1 attribute register 0x0000_0000 5.2.4.4/5-9 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 111 Reserved — — — x0_0124 0x0_0128 DDR control driver register (DDRCDR) 0x0004_0000 5.3.2.8/5-27 0x0_012C DDR debug status register (DDRDSR) 0x3300_0000 5.3.2.9/5-28 0x0_0130– Reserved — — — 0x0_01FC MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 112 GTMDR1—Timer 1 global timers mode register 0x0000 5.7.5.2/5-58 0x0_0512 GTMDR2—Timer 2 global timers mode register 0x0_0514 GTRFR1—Timer 1 global timers reference register 0xFFFF 5.7.5.3/5-60 0x0_0516 GTRFR2—Timer 2 global timers reference register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 113 GTRFR1—Timer 1 global timers reference register 0xFFFF 5.7.5.3/5-60 0x0_0616 GTRFR2—Timer 2 global timers reference register 0x0_0618 GTCPR1—Timer 1 global timers capture register 0x0000 5.7.5.4/5-60 0x0_061A GTCPR2—Timer 2 global timers capture register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 114 SMPRR_A—System mixed interrupt group A priority 0x0530_9770 8.5.9/8-18 register 0x0_0734 SMPRR_B—System mixed interrupt group B priority 0x0530_9770 8.5.10/8-19 register 0x0_0738 SEMSR—System external interrupt mask register 0x0000_0000 8.5.11/8-20 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 115 — — 0x0_090C 0x0_0910 RSR—Reset status register 0x0000_0000 4.5.1.3/4-33 0x0_0914 RMR—Reset mode register 0x0000_0000 4.5.1.4/4-34 0x0_0918 RPR—Reset protection register 0x0000_0000 4.5.1.5/4-35 0x0_091C RCR—Reset control register 0x0000_0000 4.5.1.6/4-35 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 116 Reserved, should be cleared — — — 0x0_2008 CS1_BNDS—Chip select 1 memory bounds 0x0000_0000 0x0_200C– Reserved — — — 0x0_207F 0x0_2080 CS0_CONFIG—Chip select 0 configuration 0x0000_0000 9.4.1.2/9-10 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-10 Freescale Semiconductor...
Page 117 0x0_3010 I2C1DR—I C1 data register 0x00 17.3.1.5/17-9 0x0_3014 I2C1DFSRR—I C1 digital filter sampling rate register 0x0001_0000 17.3.1.6/17-9 0x0_301C– Reserved, should be cleared — — — 0x0_30FF MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-11...
Page 118 UDSR—ULCR[DLAB] = x UART1 DMA status register 0x01 18.3.1.13/18-17 0x0_4600 URBR—ULCR[DLAB] = 0 UART2 receiver buffer register 0x00 18.3.1.1/18-5 0x0_4600 UTHR—ULCR[DLAB] = 0 UART2 transmitter holding 0x00 18.3.1.2/18-6 register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-12 Freescale Semiconductor...
Page 119 MAR—UPM address register 0x0000_0000 10.3.1.3/10-19 0x0_506C Reserved — — — 0x0_5070 MAMR—UPMA mode register 0x0000_0000 10.3.1.4/10-20 0x0_5074 MBMR—UPMB mode register 0x0000_0000 10.3.1.4/10-20 0x0_5078 MCMR—UPMC mode register 0x0000_0000 10.3.1.4/10-20 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-13...
Page 120 Reserved, should be cleared — — — 0x0_6FFF Serial Peripheral Interface (SPI) 0x0_7000– — — — Reserved, should be cleared 0x0_701F 0x0_7020 SPMODE—SPI mode register 0x0000_0000 19.4.1.1/19-9 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-14 Freescale Semiconductor...
Page 121 DMANDAR1—DMA 1 next descriptor address register 0x0000_0000 12.3.8.7/12-14 0x0_8200 DMAMR2—DMA 2 mode register 0x0000_0000 12.3.8.1/12-9 0x0_8204 DMASR2—DMA 2 status register 0x0000_0000 12.3.8.2/12-11 0x0_8208 DMACDAR2—DMA 2 current descriptor address register 0x0000_0000 12.3.8.3/12-12 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-15...
Page 122 POCMR2—PCI outbound comparison mask register 2 0x0000_0000 11.4.3/11-4 0x0_8448 POTAR3—PCI outbound translation address register 3 0x0000_0000 11.4.1/11-3 0x0_8450 POBAR3—PCI outbound base address register 3 0x0000_0000 11.4.2/11-3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-16 Freescale Semiconductor...
Page 123 PIEBAR1—PCI inbound extended base address register 1 0x0000_0000 13.3.2.13/13-24 0x0_8560 PIWAR1—PCI inbound window attributes register 1 0x0000_0000 13.3.2.14/13-24 0x0_8568 PITAR0—PCI inbound translation address register 0 0x0000_0000 13.3.2.11/13-22 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-17...
Page 124 USBMODE—USB device mode 0x0000_0000 16.3.2.16/16-34 0x2_31AC ENDPTSETUPSTAT—Endpoint setup status 0x0000_0000 16.3.2.17/16-35 0x2_31B0 ENDPOINTPRIME—Endpoint initialization 0x0000_0000 16.3.2.18/16-36 0x2_31B4 ENDPTFLUSH—Endpoint de-initialize 0x0000_0000 16.3.2.19/16-36 0x2_31B8 ENDPTSTATUS—Endpoint status 0x0000_0000 16.3.2.20/16-37 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-18 Freescale Semiconductor...
Page 125 0x2_4104 TSTAT—Transmit status register 0x0000_0000 15.5.3.2.2/15-38 0x2_4108 DFVLAN—Default VLAN control word 0x8100_0000 15.5.3.2.3/15-42 0x2_410C Reserved — — — 0x2_4110 TXIC—Transmit interrupt coalescing configuration register 0x0000_0000 15.5.3.2.4/15-43 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-19...
Page 126 0x2_4220 Reserved 0x0000_0000 — 0x2_4224 TBASE4—TxBD base address of ring 4 0x0000_0000 15.5.3.2.10/15-47 0x2_4228 Reserved 0x0000_0000 — 0x2_422C TBASE5—TxBD base address of ring 5 0x0000_0000 15.5.3.2.10/15-47 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-20 Freescale Semiconductor...
Page 127 0x2_4344– Reserved 0x0000_0000 — 0x2_437C 0x2_4380 RBDBPH—Rx data buffer pointer high bits 0x0000_0000 15.5.3.3.11/15-62 0x2_4384 RBPTR0—RxBD pointer for ring 0 0x0000_0000 15.5.3.3.11/15-62 0x2_4388 Reserved 0x0000_0000 — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-21...
Page 128 RBASE7—RxBD base address of ring 7 0x0000_0000 15.5.3.3.12/15-63 0x2_4440–0 Reserved 0x0000_0000 — x2_44BC 0x2_44C0 TMR_RXTS_H*—Rx timer time stamp register high 0x0000_0000 15.5.3.3.13/15-63 0x2_44C4 TMR_RXTS_L*—Rx timer time stamp register low 0x0000_0000 15.5.3.3.13/15-63 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-22 Freescale Semiconductor...
Page 129 — — — 0x2_453C IFSTAT—Interface status register Special 0x0000_0000 15.5.3.5.12/15-76 0x2_4540 MACSTNADDR1—Station address register, part 1 0x0000_0000 15.5.3.5.13/15-77 0x2_4544 MACSTNADDR2—Station address register, part 2 0x0000_0000 15.5.3.5.14/15-78 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-23...
Page 130 MAC15ADDR2—MAC exact match address 15, part 2 0x0000_0000 0x2_45C0– Reserved 0x0000_0000 — 0x2_467C eTSEC1 Transmit and Receive Counters 0x2_4680 TR64—Transmit and receive 64-byte frame counter 0x0000_0000 15.5.3.6.1/15-80 register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-24 Freescale Semiconductor...
Page 131 15.5.3.6.26/15-92 0x2_46E8 TMCA—Transmit multicast packet counter register 0x0000_0000 15.5.3.6.27/15-93 0x2_46EC TBCA—Transmit broadcast packet counter register 0x0000_0000 15.5.3.6.28/15-93 0x2_46F0 TXPF—Transmit PAUSE control frame counter register 0x0000_0000 15.5.3.6.29/15-94 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-25...
Page 132 IGADDR5—Individual/group address register 5 0x0000_0000 0x2_4818 IGADDR6—Individual/group address register 6 0x0000_0000 0x2_481C IGADDR7—Individual/group address register 7 0x0000_0000 0x2_4820– Reserved, should be cleared — — — 0x2_487C MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-26 Freescale Semiconductor...
Page 133 TMR_PRSC*—Timer prescale 0x0000_0002 15.5.3.10.10/15-119 0x2_4E2C Reserved 0x0000_0000 — 0x2_4E30 TMR_OFF_H*—Timer offset high 0x0000_0000 15.5.3.10.11/15-119 0x2_4E34 TMR_OFF_L*—Timer offset low 0x0000_0000 15.5.3.10.11/15-119 0x2_4E38-0 Reserved — — — x2_4E3F MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-27...
Page 134 ISR—Interrupt status register 0x0000_0000 14.6.4.3/14-70 _0000_0000 0x3_1018 ICR—Interrupt clear register 0x0000_0000 14.6.4.4/14-71 _0000_0000 0x3_1020 ID—Identification register 0000_0000 14.6.4.5/14-73 _0000_00A0 0x3_1028 EUASR—EU assignment status register 0xF0F0_F0F0 14.6.4.1/14-67 _00FF_F0F0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-28 Freescale Semiconductor...
Page 135 DEUK1—DEU key 1 register — 14.4.1.10/14-28 0x3_2408 DEUK2—DEU key 2 register — 14.4.1.10/14-28 0x3_2410 DEUK3—DEU key 3 register — 14.4.1.10/14-28 0x3_2800– DEU FIFO 0x0000_0000 14.4.1.11/14-28 0x3_2FFF _0000_0000 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-29...
Page 136 0x0000_0000 14.4.2.7/14-35 _0000_0000 0x3_6038 MDEUICR—MDEU interrupt control register 0x0000_0000 14.4.2.8/14-36 _0000_1000 0x3_6040 MDEU ICV size register 0x0000_0000_0 14.4.2.9/14-37 000_0000 0x3_6050 MDEUEMR—MDEU end-of-message register 0x0000_0000 14.4.2.10/14-38 _0000_0000 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-30 Freescale Semiconductor...
Page 137 Depends on the reset configuration word high values. See Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value”, for details. Depends on the reset configuration word high values. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 2-31...
Page 138 Memory Map MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 2-32 Freescale Semiconductor...
Page 139 Figure 3-2 show the external signals of the device and how the signals are grouped. Refer to the MPC8313E Integrated Processor Hardware Specifications for a pinout diagram showing pin numbers and a listing of all the electrical and mechanical specifications.
Page 140 Note that individual chapters of this document provide details for each signal, describing each signal’s behavior when asserted and negated and when the signal is an input or an output. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 141: Signal Descriptions
Local Bus LGPL2/LOE/LFRE Interface IIC1_SCL/CKSTOP_IN Interface 4 Signals LGPL3/LFWP IIC2_SCL/GPIO[11] 58 Signals LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK[0:1] LA[0:4]/MSRCID[0:4]/GPIO[0:4] LA[5]/MDVAL/GPIO[5] LA[6:7]/GPIO[6:7] LA[8:9]/GPIO[13:14] LA[10:25] Figure 3-1. MPC8313E Signal Groupings (1 of 2) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 142: Table Page
MDQ[0:31] DDR data 9-3/9-5 — — MDM[0:3] DDR data mask 9-3/9-5 — — MDQS[0:3] DDR data strobe 9-3/9-5 — — MBA[0:2] DDR bank select 9-3/9-5 — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 143 PCI request 2 13-3/13-5 — — PCI_GNT0 PCI grant 0 13-3/13-5 — — PCI_GNT1 PCI grant 1 13-3/13-5 CPCI_HS_LED 13-3/13-5 PCI_GNT2 PCI grant 2 13-3/13-5 CPCI_HS_ENUM 13-3/13-5 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 144 IIC2_SDA C serial data 17-1/17-3 PMC_PWR_OK/ 5-64/5-67, GPIO[10] 21-1/21-2 IIC2_SCL C serial clock 17-1/17-3 GPIO[11] 21-1/21-2 SPIMOSI SPI master-out 19-2/19-7 GTM1_TIN3/ 5-27/5-21, slave-in GTM2_TIN4/LSRCID4 10-2/10-5, /GPIO[28] 21-1/21-2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 145 15-2/15-8 USBDR_STP/ 16-2/16-4, data 2 TSEC_1588_PP3 15-2/15-8 TSEC1_TX_EN eTSEC1 transmit eTSEC1 15-2/15-8 TSEC1_1588_ 15-2/15-8 enable ALARM1 TSEC2_COL eTSEC2 collision eTSEC2 15-2/15-8 GTM1_TIN4/ 5-27/5-21, detect GTM2_TIN3/ 21-1/21-2 GPIO[15] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 146 1588 timers eTSEC 15-2/15-8 TSEC1_TXD[3] 15-2/15-8 TSEC_1588_PP1 1588 timer pulse per eTSEC 15-2/15-8 TSEC1_TXD[2] 15-2/15-8 period 1 TSEC_1588_PP2 1588 timer pulse per eTSEC 15-2/15-8 TSEC1_TXD[1] 15-2/15-8 period 2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 147 — SerDes PLL testing SD_PLL_TPD Digital test point for SGMII PHY 15-2/15-8 — — SerDes PLL testing SD_REF_CLK SerDes PLL SGMII PHY 15-2/15-8 SD_REF_CLK 15-2/15-8 reference clock MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 148 0 LWE1/LFWE1/LBS1 eLBC write enable eLBC 10-2/10-5 — — 1/FCM write enable 1/UPM byte (lane) select 1 LBCTL eLBC data buffer eLBC 10-2/10-5 — — control MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-10 Freescale Semiconductor...
Page 149 TSEC1_CRS 15-2/15-8 USBDR_TXDRXD2 USB data bus 2 16-2/16-4 TSEC1_GTX_CLK 15-2/15-8 USBDR_TXDRXD3 USB data bus 3 16-2/16-4 TSEC1_RX_CLK 15-2/15-8 USBDR_TXDRXD4 USB data bus 4 16-2/16-4 TSEC1_RX_DV 15-2/15-8 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-11...
Page 150 GTM1_TGATE3/ Timer gate 3/4 Global 5-27/5-21 LDVAL/ 10-2/10-5, GTM2_TGATE4 Timers GPIO[29]/ 21-1/21-2, SPIMISO 19-2/19-7 GTM1_TIN4/ Timer in 4/3 Global 5-28/5-24 GPIO[15]/ 21-1/21-2, GTM2_TIN3 Timers TSEC2_COL 15-2/15-8 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-12 Freescale Semiconductor...
Page 151 LA[5]/MDVAL 10-2/10-5, I/O signal 5 9-1/9-3 GPIO[6] General-purpose GPIO 21-1/21-2 LA[6] 10-2/10-5 I/O signal 6 GPIO[7] General-purpose GPIO 21-1/21-2 LA[7]/ 10-2/10-5, I/O signal 7 TSEC_1588_TRIG2 15-2/15-8 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-13...
Page 152 15-2/15-8 I/O signal 26 GPIO[27] General-purpose GPIO 21-1/21-2 TSEC2_TX_ER 15-2/15-8 I/O signal 27 GPIO[28] General-purpose GPIO 21-1/21-2 GTM1_TIN3/ 5-27/5-21, I/O signal 28 GTM2_TIN4/ 10-2/10-5, LSRCID4/SPIMOSI 19-2/19-7 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-14 Freescale Semiconductor...
Page 153 — — SYS_CR_CLK_OUT Crystal clock output Clocks 4-2/4-3 — — SYS_CLK_IN Clock input Clocks 4-2/4-3 — — USB_CR_CLK_IN USB crystal clock Clocks 4-2/4-3 — — input MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-15...
Page 154 GTM2_TGATE2/ 16-1/16-3 USBDR_DRIVE_ VBUS LSRCID2 Memory debug Debug 10-2/10-5 GTM1_TOUT1/ 5-27/5-21, source ID 2 USBDR_PCTL0 16-1/16-3 LSRCID3 Memory debug Debug 10-2/10-5 USBDR_PCTL1 16-1/16-3 source ID 3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-16 Freescale Semiconductor...
Page 155 CPCI_HS_LED CompactPCI hot 13-3/13-5 PCI_GNT1 13-3/13-5 swap LED EXT_PWR_CTRL External power 5-64/5-67 — — control GPIO[0:4] General-purpose GPIO 21-1/21-2 LA[0:4]/MSRCID[0:4] 10-2/10-5, I/O signals 0-4 9-1/9-3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-17...
Page 156 LSRCID4/SPIMOSI 19-2/19-7 GPIO[29] General-purpose GPIO 21-1/21-2 GTM1_TGATE3/ 5-27/5-21, I/O signal 29 GTM2_TGATE4/ 10-2/10-5, LDVAL/SPIMISO 19-2/19-7 GPIO[30] General-purpose GPIO 21-1/21-2 GTM1_TOUT3/ 5-27/5-21, I/O signal 30 SPICLK 19-2/19-7 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-18 Freescale Semiconductor...
Page 157 5-27/5-21 GPIO[30]/ 21-1/21-2, Timers SPICLK 19-2/19-7 GTM1_TOUT4/ Timer out 4/3 Global 5-28/5-24 GPIO[17]/ 21-1/21-2, GTM2_TOUT3 Timers TSEC2_GTX_CLK 15-2/15-8 HRESET Hard reset System 4-1/4-1 — — control MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-19...
Page 158 LGPL0/LFCLE eLBC UPM general eLBC 10-2/10-5 — — purpose line 0/Flash command latch enable LGPL1/LFALE eLBC GP line eLBC 10-2/10-5 — — 1/Flash address latch enable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-20 Freescale Semiconductor...
Page 159 9-3/9-5 — — MBA[0:2] DDR bank select 9-3/9-5 — — MCAS DDR column 9-3/9-5 — — address strobe MCK, MCK DDR differential 9-4/9-7 — — clocks MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-21...
Page 160 — PCI_CLK2 PCI clock 2 4-2/4-3 — — PCI_CLOCK/ PCI clock/PCI clock Clocks 4-2/4-3 — — PCI_SYNC_IN sync input PCI_DEVSEL PCI device select 13-3/13-5 — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-22 Freescale Semiconductor...
Page 161 15-2/15-8 15-2/15-8 A, positive data Serial receiver, lane SGMII PHY 15-2/15-8 15-2/15-8 A, negative data (complement) Serial receiver, lane SGMII PHY 15-2/15-8 15-2/15-8 B, positive data MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-23...
Page 162 Crystal clock output Clocks 4-2/4-3 — — Test clock JTAG 20-2/20-2 — — Test data in JTAG 20-2/20-2 — — Test data out JTAG 20-2/20-2 — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-24 Freescale Semiconductor...
Page 163 TSEC_MDIO Ethernet Ethernet 15-2/15-8 — — management management data in/out TSEC1_COL eTSEC1 collision eTSEC1 15-2/15-8 USBDR_TXDRXD0 16-2/16-4 detect TSEC1_CRS eTSEC11 carrier eTSEC1 15-2/15-8 USBDR_TXDRXD1 16-2/16-4 sense MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-25...
Page 164 GTM2_TOUT3/ 21-1/21-2 GPIO[17] TSEC2_RX_CLK eTSEC2 receive eTSEC2 15-2/15-8 GTM1_TIN2/ 5-28/5-24, clock GTM2_TIN1/GPIO[18] 21-1/21-2 TSEC2_RX_DV eTSEC2 receive eTSEC2 15-2/15-8 GTM1_TGATE2/ 5-28/5-24, data valid GTM2_TGATE1/ 21-1/21-2 GPIO[19] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-26 Freescale Semiconductor...
Page 165 MDVAL — UART_SOUT1 DUART serial data DUART 18-2/18-3 MSRCID0 9-1/9-3 UART_SOUT2 DUART serial data DUART 18-2/18-3 MSRCID4 9-1/9-3 USB_CLK_IN USB clock input Clocks 4-2/4-3 — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-27...
Page 166 USB next data 16-2/16-4 TSEC1_RXD[0]/ 15-2/15-8 TSEC_1588_TRIG1 USBDR_PCTL0 USB status LED 0 16-1/16-3 GTM1_TOUT1/ 5-27/5-21, control LSRCID2 10-2/10-5 USBDR_PCTL1 USB status LED 0 16-1/16-3 LSRCID3 10-2/10-5 control MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-28 Freescale Semiconductor...
Page 167: Reset Configuration Signals
3-3. The detailed interpretation of their voltage levels during reset is described in Chapter 4, “Reset, Clocking, and Initialization.” Table 3-3. Reset Configuration Signals Functional Functional Signal Name Reset Configuration Name Interface eTSEC2 TSEC2_TXD[3:0] CFG_RESET_SOURCE[0:3] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-29...
Page 168: Output Signal States During System Reset
‘0’ TSEC1_TXD[3:0] eTSEC1 transmit data 2–0 All ‘Z’ TSEC1_TX_EN eTSEC1 transmit enable ‘0’ TSEC2_GTX_CLK eTSEC2 transmit clock out ’Z’ TSEC2_TXD[3:0] eTSEC2 transmit data 6-4 All ‘Z’ MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-30 Freescale Semiconductor...
Page 169: Signals For Multiplexing
Table 3-5. Signals for Multiplexing Signal Group Multiplexing is Controlled By Table/Page eLBC (LA[0:15]/GPIO]) CFG_LBIU_MUX_EN 3-6/3-32 PCI/CPCI RCWH[PCIARB] 4.3.2.2/4-15 All others SICRL/SICRH 5.3.2.5/5-21/5.3.2.6/5-23 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 3-31...
Page 170: External Signals-Detailed Signal Descriptions
Timing This signal should be connected to pull-up or pull-down on the board. The signal needs to be valid at all times and static. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 3-32 Freescale Semiconductor...
Page 171: External Signals
PCI_CLK (PCI agent mode) cycles. Requirements An open-drain signal. An external pull-up is required. Reset State Output, driven low during power-on and hard reset flows. High impedance after reset flow completes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 172 Refer to the hardware specifications for proper resistors values to pull reset configuration signals high or low. Reset State Always input MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 173: External Clock Signals
Requirements Should be tied low if unused, for example when the clock is provided through USB_CR_CLK_IN or when derived from the system clock. Reset State Always input. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 174: Functional Description
The device has several inputs to the reset logic: • Power-on reset (PORESET) • External hard reset (HRESET) • External soft reset (SRESET) • Software watchdog reset • System bus monitor reset • Checkstop reset MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 175: Reset Causes
• Hard reset resets the entire device excluding clock logic and error capture registers. • Soft reset initializes the internal logic while maintaining the system configuration. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 176: Power-On Reset Flow
2. The system asserts PORESET and TRST, causing all registers to be initialized to their default states and most I/O drivers to be released to high-impedance. Some clock, clock enabled, and system control signals remain active. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 177 14. The PCI interface can now accept external requests, if enabled, and the boot vector fetch by the core can proceed, if enabled. The device is now in its ready state. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 178: Hard Reset Flow
Because the device does not sample the reset configuration input signals (CFG_RESET_SOURCE, CFG_CLKIN_DIV) during a hard reset flow, setting a new value on those signals (other than that set during power-on reset) has no effect. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 179: Soft Reset Flow
While the PORESET and HRESET signals are asserted, all other signal drivers connected to these signals must be in the high-impedance state. Refer to the hardware specifications for proper resistor values for pulling reset configuration signals high or low. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 180: Reset Configuration Words Source
1011 Hard-coded option 3. Reset configuration word is not loaded. 1100 Hard-coded option 4. Reset configuration word is not loaded. 1101 Reserved 1110 Reserved 1111 Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-10 Freescale Semiconductor...
Page 181: Sys_Clk_In Division
(Agent Mode) PCI_CLK Cycles μ 33 MHz 33 MHz 0000 15210 (RCW loaded from NOR Flash) μ 66 MHz 66 MHz 1000–1100 15380 (use hard coded RCW) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-11...
Page 182: Reset Configuration Words
Reset configuration word low register (RCWLR) • Reset configuration word high register (RCWHR) • Reset status register (RSR) • System PLL mode register (SPMR) Section 4.5, “Memory Map/Register Definitions.” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-12 Freescale Semiconductor...
Page 183 COREPLL Core PLL configuration. COREPLL sets the ratio between the e300 core clock and the internal csb_clk of the device. The encodings for COREPLL are given in the hardware specifications for this device. 16–31 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-13...
Page 184: System Pll Ratio
SPMF with respect to these values. Values for SPMF are as follows: Table 4-10. SPMF Maximum Values Maximum SPMF CFG_CLKIN_DIV LBCM DDRCM Value (decimal) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-14 Freescale Semiconductor...
Page 185 1 Core boot holdoff mode. The core is prevented from booting until it is configured by an external master. Boot memory space. Section 4.3.2.2.2, “Boot Memory Space (BMS),” for more information. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-15...
Page 186: Pci Host/Agent Configuration
Table 4-12. PCI Host/Agent Configuration Value RCWHR Bit Field Name Meaning (Binary) PCIHOST The device acts as a PCI agent device. The device acts as the host processor (default). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-16 Freescale Semiconductor...
Page 187: Boot Memory Space (Bms)
4-14, allow the boot sequencer to load configuration data from the serial ROM located on the I C port before the host tries to configure the device. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-17...
Page 188: Boot Rom Location
The boot ROM location reset configuration word field, shown in Table 4-15, establishes the location of boot ROM. The exact boot ROM location table to be used is defined by the setting of RCWHR[RLEXT] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-18 Freescale Semiconductor...
Page 189: Etsec1 Mode Configuration
The eTSEC1 controller operates in the RTBI protocol, using only four transmit data signals and four receive data signals. The eTSEC1 controller operates in the SGMII protocol, using the on-chip PHY. Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-19...
Page 190: Etsec2 Mode Configuration
The function of these signals can be changed by writing to this register during system initialization. See Section 5.3.2.6, “System I/O Configuration Register High (SICRH).” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-20 Freescale Semiconductor...
Page 191: E300 Core True Little Endian
GPCM, so GPCM controlled is used to read the reset configuration word from EEPROM. /LGTA should be high to avoid unintended early termination of the read cycle. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 192: Local Bus Configuration Eeprom Addresses
NAND Flash is used, or 2048 bytes if large page NAND Flash is used. The local bus controller’s registers setting will be set according to Table 4-22. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-22 Freescale Semiconductor...
Page 193: Local Bus Controller Setting When Loading Rcw
No additional EEPROMs are accessed by the boot sequencer in reset configuration mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-23...
Page 194: Eeprom Data Format In Reset Configuration Mode
EEPROM contents, including the preamble, reset configuration words and additional initialization data, and CRC. In this example, it is assumed that the EEPROM contains MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-24...
Page 195 Reset configuration word high [24–31] BYTE_EN ADDR[12–13] ADDR[14–21] ADDR[22–29] Last configuration DATA[0–7] preload command DATA[8–15] DATA[16–23] DATA[24–31] End command CRC[0–7] Cyclic redundancy CRC[8–15] check CRC[16–23] CRC[24–31] Figure 4-6. EEPROM Contents MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-25...
Page 196: Hard Coded Reset Configuration Word Low Fields Values
0 1:1 Value 1 2:1 1 2:1 1000 0100 0000100 16’b0 1001 0010 0000101 16’b0 1010 0101 0000011 16’b0 1011 0010 0000100 16’b0 1100 0101 0000100 16’b0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-26 Freescale Semiconductor...
Page 197: Hard-Coded Reset Configuration Word High Field Values
Table 4-25. Examples For Hard-Coded Reset Configuration Words Usage CFG_RESET_SOURCE[0:3] 1000 1001 1010 1011 1100 PCI_CLK (MHz) csb_clk (MHz) DDR Controller Clock (MHz) Core Clock (MHz) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-27...
Page 198 SYS_CLK_IN must be tied to quiet ground. Similarly, if USB_CLK_IN is used as the USB clock, USB_CR_CLK_IN (crystal input) must be tied to quiet ground; otherwise, USB_CLK_IN must be tied to quiet ground. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-28 Freescale Semiconductor...
Page 199 125-MHz source Figure 4-7. Clock Subsystem Block Diagram The primary clock input to this device is PCI_CLK. This clock is the reference to the system APLL. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-29...
Page 200: Clocking In Pci Host Mode
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-30...
Page 201: Configurable Clock Units
This allows for a single crystal or clock input to supply both system and USB references. The USB reference clock can be provided with a divide by 1 or 2 from these inputs (see Figure 4-7). When using the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-31...
Page 202: Reset Configuration And Status Registers Memory Map
— — 0x0_0910 Reset status register (RSR) All zeros 4.5.1.3/4-33 0x0_0914 Reset mode register (RMR) All zeros 4.5.1.4/4-34 0x0_0918 Reset protection register (RPR) All zeros 4.5.1.5/4-35 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-32 Freescale Semiconductor...
Page 203: Reset Status Register (Rsr)
C boot sequencer has failed while loading the reset configuration words. Cleared by writing a 1 to it (writing zero has no effect). 16–18 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-33...
Page 204: Reset Mode Register (Rmr)
4-9, enables a hard reset sequence on the device when the e300 core enters checkstop state. Address 0x0_0914 Access: Read/Write — CSRE Reset All zeros Figure 4-9. Reset Mode Register (RMR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-34 Freescale Semiconductor...
Page 205: Rmr Field Descriptions
0x5253_5445 to the RPR. Address 0x0_091C Access: Read/Write — SWHR — Reset All zeros Figure 4-11. Reset Control Register (RCR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-35...
Page 206: Reset Control Enable Register (Rcer)
4.5.2.1/4-37 0x0_0A04 Output clock control register (OCCR) 0x0000_80C0 4.5.2.2/4-38 0x0_0A08 System clock control register (SCCR) 0x7DDF_FFFF 4.5.2.3/4-39 0x0_0A0C– Reserved, should be cleared — — — 0x0_0AFC MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-36 Freescale Semiconductor...
Page 207: System Pll Mode Register (Spmr)
Section 4.3.1.2, “SYS_CLK_IN Division” CFG_CLKIN_DIV input signal during the reset flow. 9–15 COREPLL Core PLL configuration. See the applicable device hardware specification. 16–31 — Reserved — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-37...
Page 208: Output Clock Control Register (Occr)
Enable/Disable LCLK[0] pin clock out 0 Disable LCLK[0] 1 Enable LCLK[0] LCLK1OE Enable/Disable LCLK[1] pin clock out 0 Disable LCLK[1] 1 Enable LCLK[1] 26–31 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-38 Freescale Semiconductor...
Page 209: System Clock Control Register (Sccr)
10 USB DR clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the USB DR). 11 USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR). 12–14 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 4-39...
Page 210 PCI clock mode. Define the clock mode for all of the PCI complex - PCI and DMA. 0 PCI complex clocks are disabled. 1 PCI complex clocks are enabled. 16–31 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 4-40 Freescale Semiconductor...
Page 211: Local Access Windows Target Interface
Table 5-1. Local Access Windows Target Interface Window Number Target Interface Comments Configuration registers (IMMR) Fixed 1-Mbyte window size Local bus — Local bus — Local bus — Local bus — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 212: Local Access Windows Example
Local bus 0xA000_0000 512 Mbytes 0xC000_0000 256 Mbytes Local bus 0xFF40_0000 1 Mbyte Configuration registers (IMMR) 0xFF80_0000 8 Mbytes Local bus boot ROM Flash 4, 6, 8 Unused MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 213: Format Of Window Definitions
The number of bits used in the comparison is dictated by each window’s size attribute. When an address hits within a window, the transaction is directed to the appropriate target. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 214: Window Into Configuration Space
Internal memory map base address register (IMMRBAR) 0xFF40_0000 5.2.4.1/5-6 0x0_0004 Reserved — — — 0x0_0008 Alternate configuration base address register (ALTCBAR) 0x0000_0000 5.2.4.2/5-7 0x0_000C– Reserved — — — 0x0_001C MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 215 Depends on reset configuration word high values. See Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” details. Depends on reset configuration word high values. See Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,” for details. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 216: Local Access Register Descriptions
The IMMRBAR is shown in Figure 5-2. Offset 0x00 Access: Read/Write BASE_ADDR — Reset — Reset All zeros Figure 5-2. Internal Memory Map Registers’ Base Address Register (IMMRBAR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 217: Immrbar Bit Settings
BASE_ADDR Identifies the12 most-significant address bits of an alternate base address used for boot sequencer configuration accesses. 12–31 — Reserved. Write has no effect, read returns 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 218: Lblawbar0-Lblawbar3 Bit Settings
LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-8 defines the reset value of LBLAWBAR0[BASE_ADDR]. ‘ Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value RCWHR[BMS] BASE_ADDR Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 219: Lblawar0-Lblawar3 Bit Settings
00 / 101–111 e300c3 core boot performed from a local bus device. Local bus 8-Mbyte (22+1) ) local access window is enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 220: Pcilawbar0-Pcilawbar1 Bit Settings
PCILAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-12 defines the reset value of PCILAWBAR0[BASE_ADDR]. Table 5-12. PCILAWBAR0[BASE_ADDR] Reset Value PCILAWBAR0[BASE_ADDR] RCWHR[BMS] Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-10 Freescale Semiconductor...
Page 221: Pcilawar0-Pcilawar1 Bit Settings
PCILAWAR0[EN]. ‘ Table 5-14. PCILAWAR0[EN] Reset Value RCWHR[RLEXT]/RC PCILAWR0[EN] Description WHR[ROMLOC] Reset Value 00 /000, 011–111 e300c3 core boot not performed from a PCI device. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-11...
Page 222: Ddrlawbar0-Ddrlawbar1 Bit Settings
DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-16 defines the reset value DDRLAWBAR0. Table 5-16. DDRLAWBAR0[BASE_ADDR] Reset Value DDRLAWBAR0[BASE_ADDR] RCWHR[BMS] Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-12 Freescale Semiconductor...
Page 223: Ddrlawar0-Ddrlawar1 Bit Settings
DDRLAWBAR0[SIZE] reset value, and DDRLAWAR0 is enabled according to the value set in the reset configuration word high ROMLOC field. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-13...
Page 224: Ddrlawar0[En] Reset Value
The local bus controller has base registers that perform a similar function. The PCI interface has outbound address translation units that map the local address into an external address space. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-14 Freescale Semiconductor...
Page 225: Outbound Address Translation And Mapping Windows
“Internal Memory Map Registers Base Address Register (IMMRBAR).” The default value for the IMMRBAR is 0xFF40_0000. NOTE The internal memory map window is always the highest priority local access window. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-15...
Page 226: Accessing Internal Memory From External Masters
DDR debug status register (DDRDSR) 0x3300_0000 5.3.2.9/5-28 0x00130–0x Reserved — — — 0014C 0x00150–0x Reserved — — — 001FC Depends on the reset configuration word high configuration values. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-16 Freescale Semiconductor...
Page 227: Sgprl Bit Settings
Figure 5-11. System General Purpose Register High (SGPRH) Table 5-22 defines the bit fields of SGPRH. ‘ Table 5-22. SGPRH Bit Settings Bits Name Description 0–31 General purpose MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-17...
Page 228: Spridr Bit Settings
The system priority and configuration register (SPCR), shown in Figure 5-13, controls the priority of requests for transactions on the internal system bus. This priority is considered by the system arbiter MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-18 Freescale Semiconductor...
Page 229: Spcr Bit Settings
(for example, FIFOs in which reading a byte may advance some internal counter). 0 No performance enhancement. 1 Performance enhancement by speculative reading is enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-19...
Page 230 The level of priority can be chosen from 4 possible levels. 00 Level 0 (lowest priority) 01 Level 1 10 Level 2 11 Level 3 (highest priority) 24–31 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-20 Freescale Semiconductor...
Page 231: Sicrl Bit Settings
SICRL[Bits] Value 0b0/0b00 0b1/0b01 0b10 0b11 Value Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3 0–1 Reserved — — — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-21...
Page 232 14–19 Reserved — — — — 20–21 USBDR GTM1_TIN1/ LSRCID0 USBDR_DRIVE_VBUS — GTM2_TIN2 GTM1_TGATE1/ LSRCID1 USBDR_PWRFAULT — GTM2_TGATE2 GTM1_TOUT1 LSRCID2 USBDR_PCTL0 — — LSRCID3 USBDR_PCTL1 — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-22 Freescale Semiconductor...
Page 233: System I/O Configuration Register High (Sicrh)
TSEC1M and TSEC2M fields settings in the reset configuration word high in order to select the correct output buffer impedance for full or reduced TSEC pin mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 234: Sicrh Bit Settings
Value Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3 0–5 Reserved — — — — INTR_A IRQ3 CKSTOP_OUT — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-24 Freescale Semiconductor...
Page 235 — — TSEC1_GTX_CLK USBDR_TXDRXD2 — — TSEC1_RX_CLK USBDR_TXDRXD3 — — TSEC1_RX_DV USBDR_TXDRXD4 — — TSEC1_RXD3 USBDR_TXDRXD5 — — TSEC1_RXD2 USBDR_TXDRXD6 — — TSEC1_RXD1 USBDR_TXDRXD7 — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-25...
Page 236: Sicrh[30-31] Bit Settings
The coding of the source ID debug information is the same as the coding of the MSTR_ID field in the AEATR register of the arbiter (See Section 6.2.7, “Arbiter Event Attributes Register (AEATR)”). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-26 Freescale Semiconductor...
Page 237: Ddrcdr Field Descriptions
DDRCDR. Table 5-30. DDRCDR Field Descriptions Bits Name Description — Reserved DSO_EN 0 DDR driver software override disable 1 DDR driver software override enable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-27...
Page 238: Ddr Debug Status Register (Ddrdsr)
1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-17. DDR Debug Status Register (DDRDSR) Reset value of bits 0–9 depends on the actual state of the signals being monitored. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-28 Freescale Semiconductor...
Page 239: Ddrdsr Field Descriptions
(mcp) if the software fails to service the software watchdog timer for a certain period of time (for example, because software is lost or trapped in a loop with no controlled exit). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-29...
Page 240: Wdt Features
(mcp) • WDT prescaled/non-prescaled clock mode: The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit, which controls the divide-by-65,536 of the WDT counter. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-30 Freescale Semiconductor...
Page 241: Wdt Register Address Map
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high). Figure 5-19. System Watchdog Control Register (SWCRR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-31...
Page 242: Swcrr Bit Settings
SWCNR is a read-only register. Writes to SWCNR have no effect and terminate without transfer error exception. Offset 0x8 Access: Read only 15 16 SWCN — Reset 0 Figure 5-20. System Watchdog Count Register (SWCNR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-32 Freescale Semiconductor...
Page 243: Swcnr Bit Settings
The user should periodically write 0x556C followed by 0xAA39 to this register to prevent a software watchdog timer timeout. SWSRR[WS] can be written at any time, but returns all zeros when read. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 244: Software Watchdog Timer Unit
Waiting for 0x556C 0xAA39 / Reload Not 0x556C / Do Not Reload Not 0xAA39 / Do Not Reload Figure 5-22. Software Watchdog Timer Service State Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-34 Freescale Semiconductor...
Page 245: Modes Of Operation
According to the value of SWCRR[SWRI], the WDT timer causes a hard reset or machine check interrupt to the core. — Reset mode (SWCRR[SWRI] = 1). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-35...
Page 246 (RTLDR). It can also be programmed to generate an interrupt every second. The real time counter control register (RTCTR) is used to enable or disable the various timer functions. The real time counter event MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-36...
Page 247: Rtc Features
There is one distinct external RTC clock input signal, defined in Table 5-36. Table 5-36. RTC Signal Properties Name Port Function Reset Pull Up RTC_CLK RTC_CLK Real time clock input. — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-37...
Page 248: Rtc Memory Map/Register Definition
The register can be read at any time. Offset 0x00 Access: Read/Write — CLEN CLIN — AIM SIM Reset All zeros Figure 5-25. Real Time Counter Control Register (RTCNR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-38 Freescale Semiconductor...
Page 249: Real Time Counter Load Register (Rtldr)
RTLDR. Table 5-40. RTLDR Bit Settings Bits Name Description 0–31 CLDV Contains the 32-bit value to be loaded in the 32-bit RTC counter. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-39...
Page 250: Real Time Counter Prescale Register (Rtpsr)
0–31 CNTV RTC counter value field. RTCTR[CNTV] contains the current value of the time counter. This is a read-only field. Writes have no effect on RTCTR[CNTV]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-40 Freescale Semiconductor...
Page 251: Real Time Counter Event Register (Rtevr)
Table 5-44. RTALR Bit Settings Bits Name Description 0–31 ALRM RTC alarm value. The alarm interrupt is generated when the value of the RTC counter equals RTALR[ALRM]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-41...
Page 252: Real Time Counter Unit
— RTC disable mode (RTCNR[CLEN] = 0) When the RTC’s clock is disabled, counter maintains its old value (default). — RTC enable mode (RTCNR[CLEN] = 1) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-42 Freescale Semiconductor...
Page 253: Rtc Programming Guidelines
Additionally, the configuration, control, and status registers are described. Note that individual chapters in this reference manual describe additional specific initialization aspects for each individual block. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-43...
Page 254: Pit Overview
PIT Modes of Operation The PIT unit can operate in the following modes: • PIT enable/disable mode • PIT periodic interrupt enable/disable mode • PIT internal/external input clock mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-44 Freescale Semiconductor...
Page 255: Pit External Signal Description
Periodic interval timer prescale register (PTPSR) 0x0000_0000 5.6.5.3/5-47 0x0C Periodic interval timer counter register (PTCTR) 0x0000_0000 5.6.5.4/5-47 0x10 Periodic interval timer event register (PTEVR) 0x0000_0000 5.6.5.5/5-48 0x14–0x1F Reserved — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-45...
Page 256: Periodic Interval Timer Control Register (Ptcnr)
5-34, contains the 32-bit value to be loaded in a 32-bit PIT counter. Offset 0x04 Access: Read/Write CLDV Reset All zeros Figure 5-34. Periodic Interval Timer Load Register (PTLDR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-46 Freescale Semiconductor...
Page 257: Periodic Interval Timer Prescale Register (Ptpsr)
Description 0–31 CNTV PIT counter value field. Contains the current value of the time counter. This is a read-only field. Writes have no effect on PTCTR[CNTV]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-47...
Page 258: Periodic Interval Timer Event Register (Ptevr)
PTCNR[CLEN] = 0, the PIT cannot count and retains the old count value. PTCTR contain the PIT current value. The PIT function can be disabled if needed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-48 Freescale Semiconductor...
Page 259: Pit Operational Modes
3. Write to PTCNR to configure and start the PIT operation: PIT input clock source, periodic interrupt mask, PIT clock enable. For real-time clock programming guidelines, see Section 5.5.7, “RTC Programming Guidelines.” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-49...
Page 260: General-Purpose Timers (Gtms)
16-Bit Counter Capture TOUT4 Detection TOUT3 TOUT2 GTRFR1 TOUT1 Reference Register GTCPR1 Capture Register Timer1 Timer2 Timer3 Timer4 Registers Interface Figure 5-39. Global Timers Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-50 Freescale Semiconductor...
Page 261: Gtm Features
16-bit timers and one 32-bit timer, or two 32-bit timers. When working in the pair-cascaded mode, the cascaded GTRFR, GTCPR, and GTCNR should be referenced with 32-bit bus cycles. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-51...
Page 262: Clock Source Modes
(TGATE1, TGATE2, TGATE3, and TGATE4), and four distinct external timer output signals (TOUT1, TOUT2, TOUT3, and TOUT4). The GTM interface signals are defined in Table 5-53. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-52 Freescale Semiconductor...
Page 263 (depending on the signal state and the configured mode) after one system bus clock when working with the internal clock. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 264: Gtm Memory Map/Register Definition
0x1A Timer 2 global timers capture register (GTCPR2) 0x1C Timer 1 global timers counter register (GTCNR1) 0x0000 5.7.5.5/5-60 0x1E Timer 2 global timers counter register (GTCNR2) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-54 Freescale Semiconductor...
Page 265 The modes can be changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn] are set, they are the only bits that can be changed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-55...
Page 266 GTCNR1[CNV1]. Note: In backward compatible mode (GTCFR1[BCM] = 0) this bit is ignored. GTCFR1[GM2] bit will control the gate mode for timers 1 and 2. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-56 Freescale Semiconductor...
Page 267 The clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 268: Global Timers Mode Registers (Gtmdr1–Gtmdr)
GTCFRn[RSTn] and GTCFRn[STPn] can be modified at any time. Offset 0x10(GTMDR1) 0x20(GTMDR3) Access: Read/Write 0x12(GTMDR2) 0x22(GTMDR4) ICLK Reset All zeros – Figure 5-42. Global Timers Mode Registers (GTMDR1 GTMDR4) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-58 Freescale Semiconductor...
Page 269 11 TIN n : corresponding TIN1, TIN2, TIN3, or TIN4 pin (falling edge). Gate enable 0 The TGATE n signal is ignored. 1 The TGATE n signal is used to control the timer. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-59...
Page 270: Global Timers Reference Registers (Gtrfr1–Gtrfr)
16-bit, memory-mapped, read/write up-counters. A read cycle to a GTCNRn[CNV] fields yields the current value of the appropriate timer but does not affect the counting operation. A write cycle to a MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-60...
Page 271: Global Timers Event Registers (Gtevr1–Gtevr)
Figure 5-46. Global Timers Event Registers (GTEVR1—GTEVR4) Table 5-62 defines the bit fields of GTEVRn. Table 5-62. GTEVR n Bit Settings Bits Name Description 0–13 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-61...
Page 272: Global Timers Prescale Registers (Gtpsr1–Gtpsr)
GTMDRn SPS prescale r This gives a total prescale range from 1 (GTPSRn[PPS] = 0x00, GTMDRn[SPS] = 0x00) to 65,536 (GTPSRn[PPS] = 0xFF, GTMDR[SPS] = 0xFF). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-62 Freescale Semiconductor...
Page 273: General-Purpose Timer Units
(TGATEn) that controls the timers. The type of transition triggering the capture is selected by the corresponding GTMDRn[CE] bits. Upon a capture or reference MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 274 GTRFR1, GTCPR1, GTCNR1 GTRFR2, GTCPR2, GTCNR2 Capture Capture Timer3 Timer4 Clock Clock GTRFR3, GTCPR3, GTCNR3 GTRFR4, GTCPR4, GTCNR4 Capture Capture Figure 5-48. Timers Non-Cascaded Mode Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-64 Freescale Semiconductor...
Page 275 D[47–32] Timer3 Timer4 Clock GTRFR3, GTCPR3, GTCNR3 GTRFR4, GTCPR4, GTCNR4 connected to D[31–16] connected to D[15–0] Capture Figure 5-50. Timers Super-Cascaded Mode Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-65...
Page 276: Programming Guidelines
When the device is in either mode, the PMC is capable of placing the device into one of the supported low-power states and supporting the power management event (PME) signaling protocol. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-66 Freescale Semiconductor...
Page 277: Pmc Memory Map/Register Definition
0x00B0C Power management controller configuration register 1 (PMCCR1) 0x0000_0000 5.8.2.4/5-71 0x00B10 Power management controller configuration register 2 (PMCCR2) 0x0002_0002 5.8.2.5/5-73 0x00B14– Reserved — — — 0x00BFC MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-67...
Page 278: Power Management Controller Configuration Register (Pmccr)
If PMCMR[PMCIE] is set, the PMC interrupt request to the PowerPC core is driven. When set, bits 23–30 indicate the sources of various wake-up events. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-68 Freescale Semiconductor...
Page 279 1 to the bit location (writing zero has no effect). Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 280: Power Management Controller Mask Register (Pmcmr)
PowerPC core to exit its low power state before any transaction on the system bus occurs. Bits 23–30 are mask bits for the defined low power wake-up events. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-70...
Page 281: Power Management Controller Configuration Register 1 (Pmccr)
Access: Read/Write USE_ — STATE Reset All zeros NEXT_STATE — LLPEN PME_EN ASSERT_PME POWER_OFF — CURR_STATE Reset All zeros Figure 5-54. Power Management Controller Configuration Register 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-71...
Page 282 1 On transitions to D3 state, negate the EXT_PWR_CTRL signal to switch external power low (VDD = 0). On wake-up assert EXT_PWR_CTRL to switch VDD power on. — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-72 Freescale Semiconductor...
Page 283: Power Management Controller Configuration Register 2 (Pmccr)
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Figure 5-55. Power Management Controller Configuration Register 2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-73...
Page 284: Dynamic Power Management
Many blocks in the device can dynamically turn off clocks within the block when sections of the block are idle. This feature is always enabled and occurs automatically. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-74...
Page 285: Shutting Down Unused Blocks
This mode is referred to as D3Warm (described below). Figure 5-56 illustrates the power segmentation provided on the device. Sequencing in and out of D3Warm will be described in the following sections. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-75...
Page 286: Support Of Pci Power Management Interface Specification
It is assumed that in D3Cold all power will be removed from the device, so PCI_PME signaling is not supported from D3Cold. Instead, an MPC8313E-specific D3Warm state is defined. The difference between D3Hot and D3Warm is that in D3Hot the device’s entire core region is supplied with the nominal 1-V VDD supply.
Page 287 PCI PME# (PCI_PME). • Properly sequencing the device into and out its lowest power mode where VDD is removed to a portion of the die. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-77...
Page 288 Core is stopped with its clocks off. Core Active Negated PCIPMR1[P clocks powered down to all blocks (including owerState]= core time base) except to the interrupt unit. System operates normally. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-78 Freescale Semiconductor...
Page 289: Entering Low Power States—Core-Only Mode
The power management controller then signals the core and acknowledges it’s request to enter power down mode. Finally the QUIESCE output signal is asserted. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-79...
Page 290: Exiting Core And System Low Power States
Software is required to enable PMCI interrupt by setting PMCMR[PMCIE], otherwise exiting from low power state is not possible. NOTE It is the software’s responsibility to clear PMCER[PMCI]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-80 Freescale Semiconductor...
Page 291: Mpc8313E-Specific Pmc Low Power States
5.8.3.7 MPC8313E-Specific PMC Low Power States This section will describe the MPC8313E D0–D3 low power states, including D3Warm, from a PCI power management perspective. The sequence of entering and exiting D0–D3 states will also be described. The power management implementation assumes the following: •...
Page 292 (see Case 2). Other (for example, Same as D1 state (Case 6), except e300 transitions to Full On mode e300 decrementer from Nap state. timer, I MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-82 Freescale Semiconductor...
Page 293 PCI (PME input). Since the device is the host, PME signaling refers to external agents asserting the PCI_PME input to the device, which is one of the defined wake-up events. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 294 D0 state into the PCI configuration registers (PCIPMR1[Power_State] = 00. This action will cause an interrupt to the e300 (D1–D3Hot) or cause the PMC to begin the wake-up process (D3Warm). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-84...
Page 295: Mpc8313E Low Power Sequencing
The following sections describe the sequence of events that occur when entering or exiting the device’s lowest power state (D3Warm). Host and agent cases are described separately. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 296 (eTSEC magic packet, USB, GPIO internal timer, external interrupt) by writing a “1” in the appropriate PMCMR[] mask register bit. 2. The PCI device driver executes code to save any MPC8313E context that would not otherwise survive the transition to the new power state (any MPC8313E context beyond what e300 software would configure on reset).
Page 297 4. The device detects the external agent’s PowerState change by polling the agent’s configuration registers. This process is repeated until all external agents are in their low power states. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 298 PCIPMR1[Power_State] in the device PCI PME context block to “00” (D0). This change will be reflected in the PMCCR1[NEXT_STATE] register bits in the PMC module. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-88 Freescale Semiconductor...
Page 299 12. The PMCCR1[CURR_STATE] register field is updated to reflect the new active state. This update is reflected in the PCIPMR1[Power_State] field indicating to the PCI host that the device has returned to its active state. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-89...
Page 300: Pmc External Power Supply Control
Figure 5-58 Figure 5-59. The use of the PMCCR2[RCNT] and PMCCR2[PDCNT] timer fields will allow calibration of the device to the switching characteristics of the power switch. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-90 Freescale Semiconductor...
Page 301 VDDC VDDAC EXT_PWR_CTRL VDD VDDA External Host PCI_PME PCI_PME MPC8313E Host GPIO VAUX Control Figure 5-59. Example VDD Control of Device as Host MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 5-91...
Page 302: Low-Power Considerations
This is mainly to prevent PMC from waking up in Host mode if there are inadvertent changes made to the PCIPMCR1[Power_State] register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-92 Freescale Semiconductor...
Page 303: Core Disable In Low Power Mode
In general, EXT_PWR_CTRL should only be toggled when going to D3Warm. This is according to general MPC8313E definitions for power levels. However, the implementation is flexible and allows for the assertion of EXT_PWR_CTRL even in D1 or D2 if desired.
Page 304 By following this flow, the e300 core remains in low power state while the rest of the system is operational, and does not get out of this state as a result of any interrupt or time-based event. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 5-94...
Page 305: Arbiter Overview
Maximum number of consecutive transactions can be limited by programming arbiter configuration register. See Section 6.2.1, “Arbiter Configuration Register (ACR),” for more details. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 306: Arbiter Memory Map/Register Definition
Note that the reset value of COREDIS and bits 10–11 are determined from reset configuration word. (See Section 4.3.2, “Reset Configuration Words,” for more details on reset configuration word.) Figure 6-1. Arbiter Configuration Register (ACR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 307 110 7 consecutive transactions 111 8 consecutive transactions Note: It is recommended not to program this field for more than four consecutive transactions. 24–25 — Write reserved, read = 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 308: Arbiter Timers Register (Atr)
When ATO = n, the timeout cycle is n*128. 0000 Reserved 0001 128 clock cycles 0002 256 clock cycles 0003 384 clock cycles FFFF 8355840 clock cycles MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 309 Specifies, whether address tenure time out will be reported in arbiter event registers. 0 Address time out isn’t reported in arbiter event registers. 1 Address time out is reported in arbiter event registers. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 310: Arbiter Event Register (Aer)
1 Data time out timer is expired. Address time out. Reports on address tenure time out. 0 Address time out timer is not expired. 1 Address time out timer is expired. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 311: Arbiter Interrupt Definition Register (Aidr)
1 Data tenure time out causes MCP interrupt. Address time out. Address tenure time out interrupt definition. 0 Address tenure time out causes regular interrupt. 1 Address tenure time out causes MCP interrupt. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 312: Arbiter Mask Register (Amr)
1 Data tenure time out interrupt enabled. Address time out. Address tenure time out interrupt mask bit. 0 Address tenure time out interrupt disabled. 1 Address tenure time out interrupt enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 313: Arbiter Event Attributes Register (Aeatr)
Write reserved, read = 0 TBST Transfer burst. 0 Burst transaction. Transfer size is greater than 8 bytes 1 Single-beat transaction. Transfer size is up to 8 bytes MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 314: Arbiter Event Address Register (Aeadr)
Section 6.4.2, “Error Handling Sequence,” for more information. Figure 6-8 shows the fields of AEADR. Offset 0x1C Access: Read-only ADDR Reset All zeros Figure 6-8. Arbiter Event Address Register (AEADR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 6-10 Freescale Semiconductor...
Page 315: Arbiter Event Response Register (Aerr)
1 Data tenure time out causes reset request. Address time out. Address tenure time out interrupt definition. 0 Address tenure time out causes interrupt. 1 Address tenure time out causes reset request. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 6-11...
Page 316: Arbitration Policy
1. For every priority level a fair arbitration scheme is used (a simple round robin scheme) 2. For every priority level other than 0, one place is reserved as a place holder for lower level arbitration rings. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 6-12 Freescale Semiconductor...
Page 317: Address Bus Arbitration With Repeat
Even though repeat request can improve the page hit ratio and the overall memory bandwidth efficiency, it can increase the worst case latency of individual master. Therefore, the arbiter has programmable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 318: Address Bus Arbitration After Artry
The arbiter is responsible for tracking the following cases on the bus: • Address time out • Data time out • Transfer error • Address only transaction type • Reserved transaction type • Illegal (eciwx/ecowx) transaction type MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 6-14 Freescale Semiconductor...
Page 319: Address Time Out
Table 6-11. Address Only Transaction Type Encoding ttype[0:4] Bus Commands 00000 Clean block 00100 Flush block 01000 Sync 01100 Kill block 10000 eieio 11000 TLB Invalidate 00001 lwarx reservation set 01001 tlbsync MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 6-15...
Page 320: Reserved Transaction Type
Table 6-13. Illegal Transaction Type Encoding ttype[0:4] Bus command 10100 External control word write (ecowx) 11100 External control word read (eciwx) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 6-16 Freescale Semiconductor...
Page 321: Initialization/Applications Information
Use HRESET to reset the chip to guarantee that the information stored in AEATR and AEADR is not lost. 3. Clear all the previous events by writing ones to the AER. This register is also cleared after reset. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 6-17...
Page 322 Arbiter and Bus Monitor MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 6-18 Freescale Semiconductor...
Page 323: E300C3 Overview
Figure 7-1 shows a block diagram of the e300c3 core. Note that the e300c3 supports floating-point operations and includes two integer units. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 324 I Cache Debug/COP PLL & Clock JTAG Interface Multiplier Touch Load Buffer Core Interface Copy-Back Buffer 32-Bit Address Bus 64-Bit Data Bus Figure 7-1. e300c3 Core Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 325: E300C3 Features
(similar to other PowerPC processors). Both protocols operate coherently in systems that contain four-state caches. Although MESI is supported by the e300 core, it is not implemented on the MPC8313E. The core also supports single-beat and burst data transfers for memory accesses and supports memory-mapped I/O operations.
Page 326 — True little-endian mode for compatibility with other true little-endian devices — Critical interrupt support — Hardware support for misaligned little-endian accesses — Configurable processor bus frequency multipliers as defined in the MPC8313E Integrated Processor Hardware Specifications MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3...
Page 327 — New icbt instruction supports initialization of instruction cache — Data cache supports four-state MESI coherency protocol (not implemented on MPC8313E) — The instruction cache is blocked only until the critical load completes (hit under reloads allowed) —...
Page 328: Instruction Unit
For a more detailed overview of instruction dispatch, see Section 7.3.6, “Instruction Timing.” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 329: Branch Processing Unit (Bpu)
The e300c3 core supports all floating-point data types based on the IEEE 754 standard (normalized, denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred by software interrupt routines. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 330: Load/Store Unit (Lsu)
The core provides separate instruction and data caches and MMUs. The core also provides an efficient processor bus interface to facilitate access to main memory and other bus subsystems. The memory subsystem support functions are described in the following sections. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 331: Memory Management Units (Mmus)
Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 332: Cache Units
The core allows read operations to precede store operations (except when a dependency exists, or in cases where a MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-10...
Page 333: System Support Functions
(tben) signal. The decrementer is a 32-bit register that generates a decrementer interrupt after a MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 334: Jtag Test And Debug Interface
— The performance monitor counter registers (PMC0–PMC3) are 32-bit counters used to count software-selectable events. Each counter counts up to 128 events. UPMC0–UPMC3 provide user-level read access to these registers. They are identified in Table 7-2. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-12 Freescale Semiconductor...
Page 335: Powerpc Architecture Implementation
PowerPC architecture by the VEA. It also provides specific details about the e300 core cache implementation. • Section 7.3.4, “Interrupt Model,” describes the interrupt model of the OEA and the differences in the core interrupt model. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-13...
Page 336: Register Model
The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands for the move to/from SPR instructions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-14 Freescale Semiconductor...
Page 337 PMR 128-131 UPMLCas PMCs PMR 16-19 PMLCas PMR 144-147 These registers are e300 core implementation-specific (not defined by the PowerPC architecture). Figure 7-2. e300 Programming Model—Registers MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-15...
Page 338: Uisa Registers
XER register—The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-16 Freescale Semiconductor...
Page 339: Vea Registers
TLB miss routines. The TGPR bit is set when either an instruction TLB miss, data read miss, or data write miss interrupt is taken. The TGPR bit is cleared by an rfi instruction. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 340 Data address translation 0 Data address translation is disabled 1 Data address translation is enabled 28–29 — Reserved. Full function. Bit 29 not reserved on e300c3. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-18 Freescale Semiconductor...
Page 341: Segment Registers (Srs)
The machine status save/restore register 0 (SRR0) is used for saving the address of the instruction that caused the interrupt, and the address to return to when a Return from Interrupt (rfi) instruction is executed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-19...
Page 342 PLL configuration signals. The HID2 register enables the true little-endian mode, cache way-locking, and the additional BAT registers. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-20 Freescale Semiconductor...
Page 343 Once qack assertion is detected, the processor enters sleep mode after several processor clocks. At this point, the system logic may turn off the PLL by first configuring pll_cfg[0:6] to PLL bypass mode, then disabling sysclk . MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-21...
Page 344 PLRU bits to point to way L0 of each set. For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive mtspr operations. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-22 Freescale Semiconductor...
Page 345 Table 7-3. Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out hreset ECLK SBCLK clk_out Asserted Bus clock (small pulse for every rising edge of sysclk) Negated Clock output off Core clock/2 Core clock Bus clock MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-23...
Page 346 Enable BIU pipeline extension.This bit enables the bus interface unit pipeline extension. 0 BIU pipeline extension disabled; 1 level pipeline 1 BIU pipeline extension enabled; 1-1/2 level pipeline MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-24 Freescale Semiconductor...
Page 347 0 through way 2 locked in e300c3. way 0 through way 2 locked in e300c3. Setting HID0[DLOCK] will lock all ways. 27–31 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-25...
Page 348: Instruction Set And Addressing Modes
TLBs, and the segment registers. — Move to/from SPR instructions — Move to/from MSR — Move to/from PMR — Synchronize — Instruction synchronize MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-26 Freescale Semiconductor...
Page 349: Implementation-Specific Instruction Set
The core implements the following instruction which is added to support critical interrupts (also supported on the G2_LE). This is a supervisor-level, context synchronizing instruction. — Return from Critical Interrupt (rfci) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-27...
Page 350: Cache Implementation
The instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware invalidation capability is provided to support cache maintenance. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-28...
Page 351 To support this feature, the shared signal, shd, has been added to the bus interface. Although the MESI protocol is supported by the e300 core, it is not implemented on MPC8313E. The following four states indicate the state of the cache block: •...
Page 352: Instruction And Data Cache Way-Locking
However, in many cases there is no attempt to re-execute the instruction. This method of recognizing and handling interrupts sequentially guarantees that interrupts are recoverable. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-30 Freescale Semiconductor...
Page 353: Implementation-Specific Interrupt Model
Synchronous/Asynchronous Precise/Imprecise Interrupt Type Asynchronous, nonmaskable Imprecise Machine check System reset Asynchronous, maskable Precise External interrupt Decrementer System management interrupt Critical interrupt Synchronous Precise Instruction-caused interrupts MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-31...
Page 354 • The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note that PowerPC little-endian mode is not supported on the e300 core. • The operand of dcbz is in memory that is write-through-required or caching-inhibited. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-32 Freescale Semiconductor...
Page 355 Occurs when the address (bits 0–29) in the IABR matches the next instruction to complete address in the completion unit, and IABR[30] is set. Note that the e300 core also implements breakpoint IABR2, which functions identically to IABR. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-33...
Page 356: Memory Management
Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most recently used page table MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-34...
Page 357: Instruction Timing
FPU, allowing up to three instructions to execute in the FPU concurrently. The FPU pipeline stages are multiply, add, and round-convert. The LSU has two MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 358: Core Interface
The core interface is specific for each processor core implementation. The MPC8313E contains an internal coherent system bus (CSB) that interfaces the processor core to the peripheral logic. This internal bus is very similar in function to the external 60x bus interface on the MPC603e.
Page 359: Memory Accesses
), checkstop signals, performance monitor signal (pm_event_in) via the PM counters, and both soft reset and hard reset signals. They are used to interrupt and, under various conditions, to reset the core. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-37...
Page 360: Debug Features
The ext_halt input pin can be used to force the core into halted state. The halted state may be a hardstop, conditional upon the HARDSTOP condition being set through the JTAG/debug interface MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-38...
Page 361: Differences Between Cores
Instruction cache way — The e300 core can protect locked ways in the instruction cache protection from invalidation; the G2_LE does not support instruction cache way protection. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 7-39...
Page 362 These are optional instructions in the PowerPC architecture. Reduced pin mode removed Reduced pin mode available Reduced pinout mode and the signal redpinmode will not be supported in the e300 core. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 7-40 Freescale Semiconductor...
Page 363: Ipic Introduction
Software watchdog timer (WDT) • C controllers (I C1 and I • SPI controller (SPI) • Power management controller (PMC) • General-purpose I/O controller (GPIO) • External pins (IRQ[0:4]) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 364 (SIVCR, SCVCR or SMVCR). In response to this read, the IPIC unit returns the vector (associated with the interrupt source) to the interrupt handler routine. In addition, the handler can vectorize different branches of interrupt handling. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 365 System Bus Arbiter Global Timers 1 Controller Global Timers 2 DDR SDRAM Controller GPIO Enhanced Local Bus Controller IRQ[0:4] Security Engine Figure 8-1. Interrupt Sources Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 366: Ipic Features
IPIC; the interrupts are sent to the PowerPC core. The DMA controller can optionally (depending on the programming of the DMA registers) steer its interrupt to the PCI host through the PCI_INTA signal. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 367: Core Disable Mode
Negated—There is no incoming interrupt from that source. Timing Assertion—All of these inputs can be asserted completely asynchronously. Negation—Interrupts programmed as level-sensitive must remain asserted until serviced. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 368: Ipic Memory Map/Register Definition
System internal interrupt pending register (SIPNR_H) All zeros 8.5.3/8-11 0x0C System internal interrupt pending register (SIPNR_L) All zeros 8.5.3/8-11 0x10 System internal interrupt group A priority register (SIPRR_A) 0x0530_9770 8.5.4/8-13 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 369: System Global Interrupt Configuration Register (Sicfr)
— MPSB MPSA — IPSD IPSC IPSB IPSA — HPIT — Reset All zeros Figure 8-2. System Global Interrupt Configuration Register (SICFR) Table 8-4 defines the bit fields of SICFR. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 370 01 smi request is asserted to the core for HPI. 10 cint request is asserted to the core for HPI. 11 Reserved. 24–31 — Write ignored, read = 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 371: System Global Interrupt Vector Register (Sivcr)
Interrupt ID Number Interrupt Meaning Interrupt Vector Error (no interrupt) 0b000_0000 1–8 Reserved 0b000_0001–0b000_1000 UART1 0b000_1001 UART2 0b000_1010 0b000_1011 eTSEC1 1588 timer 0b000_1100 eTSEC2 1588 timer 0b000_1101 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 372 0b100_0000 0b100_0001 0b100_0010 Reserved 0b100_0011 RTC ALR 0b100_0100 0b100_0101 0b100_0110 0b100_0111 GTM4 0b100_1000 GTM8 0b100_1001 GPIO 0b100_1010 Reserved 0b100_1011 0b100_1100 0b100_1101 GTM2 0b100_1110 GTM6 0b100_1111 0b101_0000 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-10 Freescale Semiconductor...
Page 373 SIMSR_H. Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments Bits Field TSEC1 Tx TSEC1 Rx TSEC1 Err TSEC2 Tx TSEC2 Rx TSEC2 Err USB DR 7–23 — UART1 UART2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-11...
Page 374 SIPNR_L fields. Note that these field assignments are also valid for SIFCR_L and SIMSR_L. Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments Bits Field RTC SEC — RTC ALR GTM4 GTM8 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-12 Freescale Semiconductor...
Page 375: System Internal Interrupt Group A Priority Register (Siprr_A)
Tx), TSEC2 receive request (TSEC2 Rx) TSEC2 transmit/receive error (TSEC2 Err), USB DR, internal interrupt signals. For more information, see Section 8.6.3, “Internal Interrupts Group Relative Priority.” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-13...
Page 376: System Internal Interrupt Group D Priority Register (Siprr_D)
24 25 27 28 SYSD0P SYSD1P SYSD2P SYSD3P SYSD4P SYSD5P SYSD6P SYSD7P — — Reset 0 Figure 8-7. System Internal Interrupt Group D Priority Register (SIPRR_D) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-14 Freescale Semiconductor...
Page 377: System Internal Interrupt Mask Register (Simsr_H And Simsr_L)
Offset 0x20 Access: Read/write n (Implemented bits are listed in Table 8-7.) Reset All zeros Figure 8-8. System Internal Interrupt Mask Register (SIMSR_H) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-15...
Page 378: System Internal Interrupt Control Register (Sicnr)
8-10, defines the IPIC output interrupt type (int, cint, or smi) in the SYSA0–SYSA1 and SYSD0–SYSD1 priority positions. All other priority positions assert int to the core. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-16 Freescale Semiconductor...
Page 379 10 cint request is asserted to the core for SYSA0. 11 Reserved. 26–27 SYSA1T Same as SYSA0T, but for SYSA1T 28–31 — Write ignored, read = 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-17...
Page 380: System External Interrupt Pending Register (Sepnr)
24 25 27 28 MIXA0P MIXA1P MIXA2P MIXA3P — MIXA4P MIXA5P MIXA6P MIXA7P — Reset 0 Figure 8-12. System Mixed Interrupt Group A Priority Register (SMPRR_A) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-18 Freescale Semiconductor...
Page 381: System Mixed Interrupt Group B Priority Register (Smprr_B)
24 25 27 28 MIXB0P MIXB1P MIXB2P MIXB3P — MIXB4P MIXB5P MIXB6P MIXB7P — Reset 0 Figure 8-13. System Mixed Interrupt Group B Priority Register (SMPRR_B) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-19...
Page 382: System External Interrupt Mask Register (Semsr)
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0) Figure 8-14. System External Interrupt Mask Register (SEMSR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-20 Freescale Semiconductor...
Page 383: System External Interrupt Control Register (Secnr)
MIXA0T MIXA1T — Reset All zeros EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7 — Reset All zeros Figure 8-15. System External Interrupt Control Register (SECNR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-21...
Page 384: System Error Status Register (Sersr)
SERSR bit. Offset 0x40 Access: Read/write INT n (Implemented bits are listed in Table 8-21) Reset All zeros Figure 8-16. System Error Status Register (SERSR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-22 Freescale Semiconductor...
Page 385: System Error Mask Register (Sermr)
SERMR bit although no MCP request is passed to the core in this case. The SERMR can be read by the user at any time. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 386: System Error Control Register (Sercr)
MCP route. Route MCP request to either MCP_OUT or PCI_INTA (in core disable mode). 0 MCP routed to PCI_INTA (in core disable mode). 1 MCP routed to MCP_OUT (in core disable mode). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-24 Freescale Semiconductor...
Page 387: System Internal Interrupt Force Registers (Sifcr_H And Sifcr_L)
SIFCR x bit. SIFCR x bit positions are not changed according to their relative priority. Writes to unimplemented (reserved) bits are ignored; read = 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-25...
Page 388: System External Interrupt Force Register (Sefcr)
SERSR bit). The SERFR can be read by the user at any time. Offset 0x5C Access: Read/write INT n (Implemented bits are listed in Table 8-21.) Reset All zeros Figure 8-22. System Error Status Register (SERFR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-26 Freescale Semiconductor...
Page 389: System Critical Interrupt Vector Register (Scvcr)
System Management Interrupt Vector Register (SMVCR) SMVCR, shown in Figure 8-24, contains a 7-bit code (Table 8-30) representing the unmasked system management interrupt (SMI) source of the highest priority level. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-27...
Page 390: Interrupt Types
IPIC, informing the processor of error conditions, assertion of the external MCP request, and other conditions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-28 Freescale Semiconductor...
Page 391: Interrupt Configuration
PowerPC core until software can handle them. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 392: Internal Interrupts Group Relative Priority
Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed but cannot be changed dynamically. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-30...
Page 393: Highest Priority Interrupt
MIXB1 (Grouped) MIXB2 (Grouped) MIXB3 (Grouped) MIXB1 (Spread) SYSA0 (Grouped) SYSA1 (Grouped) SYSA2 (Grouped) SYSA3 (Grouped) MIXA2 (Spread) SYSA4 (Grouped) SYSA5 (Grouped) SYSA6 (Grouped) SYSA7 (Grouped) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-31...
Page 394 SYSD4 (Grouped) SYSD5 (Grouped) SYSD6 (Grouped) SYSD7 (Grouped) MIXB4 (Spread) GTM4 Reserved SYSA0 (Spread) GTM8 Reserved SYSD0 (Spread) Reserved GPIO MIXA5 (Spread) Reserved Reserved SYSA1 (Spread) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-32 Freescale Semiconductor...
Page 395 SYSA3 (Spread) Reserved Reserved SYSD3 (Spread) Reserved Reserved MIXB6 (Spread) GTM3 Reserved SYSA4 (Spread) GTM7 Reserved SYSD4 (Spread) Reserved Reserved MIXA7 (Spread) Reserved Reserved SYSA5 (Spread) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-33...
Page 396: Masking Interrupt Sources
When an interrupt source has multiple interrupting events, the user can individually mask these events by programming a mask register within that particular block. Table 8-31 shows which interrupt sources have multiple interrupting events. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-34 Freescale Semiconductor...
Page 397: Interrupt Vector Generation And Calculation
The PIC supports the non-maskable machine check interrupts. When an error interrupt signal is received, the interrupt controller indicates the source by setting the corresponding SERSR bit. These sources are listed in Table 8-21. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 8-35...
Page 398 Integrated Programmable Interrupt Controller (IPIC) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 8-36 Freescale Semiconductor...
Page 399 ‘logical bank’ refers to one of the four or eight sub-banks in each SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address (MBA) pins during a memory access. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 400 — Unbuffered and registered DRAM modules • Open page management (dedicated entry for each logical bank) • Automatic DRAM initialization sequence or software-controlled initialization sequence • Automatic DRAM data initialization MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 401 All zeros MCAS Column address strobe MA[14:0] Address bus All zeros MBA[0:2] Logical bank address All zeros MCS[0:1] Chip selects All ones Write enable MRAS Row address strobe MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 402 A8 (alternate AP for DDR) MBA2 MBA2 MBA1 MBA1 MBA0 MBA0 Auto-precharge for DDR signaled on A10 when DDR_SDRAM_CFG[PCHB8] = 0. Auto-precharge for DDR signaled on A8 when DDR_SDRAM_CFG[PCHB8] = 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 403 TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM assert coincident with the data on clock edge n + m . See the JEDEC DDR SDRAM specification for more information. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 404 Section 9.4.1.6, “DDR SDRAM Timing Configuration 2 (TIMING_CFG_2),” and Section 9.4.1.3, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).” High impedance—MRAS is always driven unless the memory controller is disabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 405: Clock Interface Signals
Meaning clocks. A clock edge is seen by the SDRAM when the true and complement cross. Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 406: Debug Signals
9.4.1.3/9-11 0x104 TIMING_CFG_0—DDR SDRAM timing configuration 0 0x0011_0105 9.4.1.4/9-12 0x108 TIMING_CFG_1—DDR SDRAM timing configuration 1 All zeros 9.4.1.5/9-14 0x10C TIMING_CFG_2—DDR SDRAM timing configuration 2 All zeros 9.4.1.6/9-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 407: Register Descriptions
Offset 0x000, 0x008 Access: Read/Write 15 16 23 24 — SA n — EA n Reset All zeros Figure 9-2. Chip Select Bounds Registers (CS n _BNDS) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 408 Chip select n enable 0 Chip select n is not active 1 Chip select n is active and assumes the state set in CS n _BNDS. 1–7 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-10 Freescale Semiconductor...
Page 409 DDR SDRAM timing configuration register 3, shown in Figure 9-4, sets the extended refresh recovery time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-11...
Page 410 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 9-5. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-12 Freescale Semiconductor...
Page 411 000 Reserved 100 4 clocks 001 1 clock 101 5 clocks 010 2 clocks 110 6 clocks 011 3 clocks 111 7 clocks 16–19 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-13...
Page 412 Reset All zeros Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) Table 9-10 describes TIMING_CFG_1 fields. Table 9-10. TIMING_CFG_1 Field Descriptions Bits Name Description — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-14 Freescale Semiconductor...
Page 413 1011 6 clocks 0100 2.5 clocks 1100 6.5 clocks 0101 3 clocks 1101 7 clocks 0110 3.5 clocks 1110 7.5 clocks 0111 4 clocks 1111 8 clocks MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-15...
Page 414 21 22 23 25 26 — ADD_LAT — WR_LAT — RD_TO_PRE WR_DATA_DELAY — CKE_PLS FOUR_ACT Reset All zeros Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-16 Freescale Semiconductor...
Page 415 010; for DDR1 with burst length of 8, must be set to 100. 000 Reserved 100 4 cycles 001 1 cycle 101–111 Reserved 010 2 cycles 011 3 cycles MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-17...
Page 416: Ddr Sdram Control Configuration (Ddr_Sdram_Cfg)
DYN_PWR 8_BE NCAP — Reset 24 25 MEM_HAL 2T_EN BA_INTLV_CTL — x32_EN PCHB8 HSE — Reset All zeros Figure 9-8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-18 Freescale Semiconductor...
Page 417 If one of these devices is used, then this bit needs to be set if auto precharge is used. 0 DRAMs in system support concurrent auto-precharge. 1 DRAMs in system do not support concurrent auto-precharge. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-19...
Page 418 DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL reset is required, then the controller should be forced to enter and exit self-refresh after the controller is enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-20 Freescale Semiconductor...
Page 419 01 Assert ODT to internal IOs only during writes to DRAM 10 Assert ODT to internal IOs only during reads to DRAM 11 Always keep ODT asserted to internal IOs 11–15 — Reserved. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-21...
Page 420: Ddr Sdram Mode Configuration (Ddr_Sdram_Mode)
9-10, sets the values loaded into the DDR’s mode registers. Offset 0x118 Access: Read/Write 15 16 ESDMODE SDMODE Reset All zeros Figure 9-10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-22 Freescale Semiconductor...
Page 421 DDR’s extended mode 2 and 3 registers (for DDR2). Offset 0x11C Access: Read/Write 15 16 ESDMODE2 ESDMODE3 Reset All zeros Figure 9-11. DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-23...
Page 422: Ddr Sdram Mode Control Register (Ddr_Sdram_Md_Cntl)
NOTE Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only one of these fields can be set at a time. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-24 Freescale Semiconductor...
Page 423 0 Indicates that no precharge all command needs to be issued. 1 Indicates that a precharge all command is ready to be issued. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-25...
Page 424 — Selects logical bank — Table 9-16 MD_VALUE Value written to mode — Only bit five is — register significant. See Table 9-16 CKE_CNTL Table 9-16 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-26 Freescale Semiconductor...
Page 425: Ddr Sdram Interval Configuration (Ddr_Sdram_Interval)
DDR_DATA_INIT fields. Table 9-19. DDR_DATA_INIT Field Descriptions Bits Name Description 0–31 INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT] is set. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-27...
Page 426: Ddr Sdram Clock Control (Ddr_Sdram_Clk_Cntl)
Table 9-21. DDR_INIT_ADDR Field Descriptions Bits Name Description 0–31 INIT_ADDR Initialization address. Represents the address that is used for the automatic CAS to preamble calibration at POR. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-28 Freescale Semiconductor...
Page 427: Ddr Ip Block Revision 1 (Ddr_Ip_Rev)
Table 9-23. DDR_IP_REV2 Field Descriptions Bits Name Description 0–7 — Reserved 8–15 IP_INT IP block integration options 16–23 — Reserved 24–31 IP_CFG IP block configuration options MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-29...
Page 428 Programmable parameters allow for a variety of memory organizations and timings. The controller allows as many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-30 Freescale Semiconductor...
Page 429 This delay is implemented in the controller for both reads and writes. The address and command interface is also source synchronous, although 1/4 cycle adjustments are provided for adjusting the clock alignment. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-31...
Page 430 The DDR memory controller drives 15 address pins, but in this example the DDR SDRAM devices use only 12 bits. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-32 Freescale Semiconductor...
Page 431: Ddr Sdram Interface Operation
The data path to individual physical banks is bits wide. The DDR memory controller supports physical bank sizes from 16 Mbytes to 512 Mbytes. The physical banks can MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 432: Supported Ddr Sdram Organizations
32 Mbits × 16 13 × 10 × 2 128 Mbytes 256 Mbytes 1 Gbits 128 Mbits × 8 14 × 11 × 2 512 Mbytes 1 Gbyte MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-34 Freescale Semiconductor...
Page 433: Ddr Sdram Address Multiplexing
Table 9-30 show the address bit encodings for each DDR SDRAM configuration. The address presented at the memory controller signals MA[14:0] use MA[14] as the msb MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-35...
Page 434 11 10 9 10 x 2 MCAS 12 x MRAS 11 10 9 9 x 2 MCAS 12 x MRAS 11 10 9 8 x 2 MCAS MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-36 Freescale Semiconductor...
Page 435 11 10 9 10 x MCAS 12 x MRAS 11 10 9 9 x 2 MCAS 12 x MRAS 11 10 9 8 x 2 MCAS MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-37...
Page 436 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-38 Freescale Semiconductor...
Page 437 9 8 7 6 5 4 3 2 1 0 13 x 10 MRAS 12 11 10 9 MCAS 13 x 10 MRAS 12 11 10 9 MCAS MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-39...
Page 438: Jedec Standard Ddr Sdram Interface Commands
Parameters such as mode register data, MCAS latency, burst length, and burst type, are set by software in DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-40...
Page 439: Ddr Sdram Interface Timing
MDM[0:3]. NOTE If a second read or write is pending, reads shorter than four beats are not terminated early even if some data is irrelevant. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-41...
Page 440 SDRAM Timing Configuration 1 (TIMING_CFG_1),” Section 9.4.1.6, “DDR SDRAM Timing Configuration 2 (TIMING_CFG_2),” Section 9.4.1.3, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)”) and be kept in the DDR memory controller configuration register space. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-42 Freescale Semiconductor...
Page 441 MRAS MCAS MA n CASLAT MDQ n D1 D2 D3 D1 D2 MDQS Figure 9-23. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-43...
Page 442 MA n MDQ n D1 D2 D3 D1 D2 D1 D2 D3 D1 D2 MDQS MDM[0:3] Figure 9-25. DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-44 Freescale Semiconductor...
Page 443: Clock Distribution
SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles. SDRAM Clock MRAS MCAS MA n Code Code MBA n MDQ n MDQS Figure 9-27. DDR SDRAM Mode-Set Command Timing MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-45...
Page 444: Ddr Sdram Registered Dimm Mode
SDRAM clock cycle after the command is launched. The delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-46...
Page 445: Ddr Sdram Refresh
3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by its chip select) to refresh one row in each logical bank of the selected physical bank. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 446: Ddr Sdram Refresh Timing
DDR memory controller can be configured to take advantage of self-refreshing SDRAMs or to provide no refresh support. Self-refresh support is enabled with the SREN memory control parameter. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-48...
Page 447 TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. A penalty of 1 cycle is shown in Figure 9-31. Mem Bus Clock COMMAND Figure 9-31. DDR SDRAM Power-Down Mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-49...
Page 448: Self-Refresh In Sleep Mode
0:3The DDR memory controller uses data masks to prevent all unintended full double words from writing to SDRAM. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-50...
Page 449: Page Mode And Logical Bank Retention
Also, better performance can be obtained using more banks, especially in systems which use many different channels. Page mode is disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-51...
Page 450 Control configuration SREN NCAP 9.4.1.7/9-18 RD_EN 2T_EN SDRAM_TYPE BA_INTLV_CTL DYN_PWR x32_EN 32_BE 8_BE DDR_SDRAM_CFG_2 Control configuration DQS_CFG NUM_PR 9.4.1.8/9-21 ODT_CFG D_INIT DDR_SDRAM_MODE Mode configuration ESDMODE 9.4.1.9/9-22 SDMODE MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-52 Freescale Semiconductor...
Page 451: Programming Differences Between Memory Types
Should be set according to the specifications for the 9.4.1.5/9-14 Activate Timing memory used (t DDR2 Should be set according to the specifications for the memory used (t MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-53...
Page 452 Should be set to CAS latency – 1 cycle. For example, if the CAS latency if 5 cycles, then this field should be set to 100 (4 cycles). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-54 Freescale Semiconductor...
Page 453: Ddr Sdram Initialization Sequence
After configuration of all parameters is complete, system software must set DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 μs must elapse after DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 9-55...
Page 454 If the bypass initialization mode is used, then software can initialize the memory through the DDR_SDRAM_MD_CNTL register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 9-56 Freescale Semiconductor...
Page 455 LWE[0:1] Local Address LA[0:25] LALE Address and LPBSE Local Data Data Machine LDVAL Transfer Acknowledge LSRCID[0:4] LAD[0:15] LCLK[0:1] Figure 10-1. Enhanced Local Bus Controller Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-1...
Page 456 — Read-only ECC registers to verify after write operation — Boot chip-select support for 8-bit devices — Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during Flash reads and programming MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-2 Freescale Semiconductor...
Page 457: Elbc Bus Clock And Clock Ratios
(LCRR[CLKDIV]). This ratio affects the resolution of signal timing shifts in GPCM and FCM modes and the interpretation of UPM array words in UPM mode. The bus clock is driven identically onto pins, MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 458: Source Id Debug Mode
General purpose line 0 Reset_cfg LFCLE LFCLE Flash command latch enable — LGPL1/ LGPL1 General purpose line 1 Reset_cfg LFALE LFALE Flash address latch enable — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-4 Freescale Semiconductor...
Page 459 LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to the chip select for memory bank 0, which has the memory type and attributes defined by BR0 and OR0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-5...
Page 460 LGPL5 General-purpose line 5 State Asserted/Negated—One of six general purpose signals when in UPM mode, and drives a Meaning value programmed in the UPM array. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-6 Freescale Semiconductor...
Page 461 ID relating to the data transfer is indicated. In case of address debug, LSRCID[0:4] is valid only when the address on LAD consists of all physical address bits—with optional padding—for reconstructing the system address presented to the eLBC. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-7...
Page 462 All zeros 10.3.1.10/10-27 0x0B8 LTEIR—Transfer error interrupt register All zeros 10.3.1.11/10-28 0x0BC LTEATR—Transfer error attributes register All zeros 10.3.1.12/10-29 0x0C0 LTEAR—Transfer error address register All zeros 10.3.1.13/10-30 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-8 Freescale Semiconductor...
Page 463 Each register (bank) includes a memory attribute and selects the machine for memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR3[V] are cleared, and MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 464 LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus error interrupt is generated (if enabled), terminating the cycle. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-10...
Page 465: Option Registers (Or0–Or)
Boot Source OR0 Reset Value FCM (small page NAND Flash) 0000_03AE FCM (large page NAND Flash) 0000_07AE GPCM 0000_0FF7 eLBC not used as a boot source 0000_0F07 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-11...
Page 466: Address Mask
8 Mbytes 1111_1111_1100_0000_0 4 Mbytes 1111_1111_1110_0000_0 2 Mbytes 1111_1111_1111_0000_0 1 Mbyte 1111_1111_1111_1000_0 512 Kbytes 1111_1111_1111_1100_0 256 Kbytes 1111_1111_1111_1110_0 128 Kbytes 1111_1111_1111_1111_0 64 Kbytes 1111_1111_1111_1111_1 32 Kbytes MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-12 Freescale Semiconductor...
Page 467 LCS n and LWE are negated normally. LCS n and LWE are negated normally. 4 or 8 LCS n and LWE are negated one quarter bus clock cycle earlier. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-13...
Page 468 • Works in conjunction with EHTR to extend hold time on read accesses. • LCS n (only if ACS is not equal to 00) and LWE signals are negated one cycle earlier during writes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-14...
Page 469 Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared. Figure 10-4. Option Registers (OR n ) in FCM Mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-15...
Page 470 The write-enable is asserted 0.5 clock cycles after any command, address, or data. The write-enable is asserted 1 clock cycle after any command, address, or data. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-16 Freescale Semiconductor...
Page 471 • Works in conjunction with CBT to extend the wait time for read/busy status sampling by 16 clock cycles. • Works in conjunction with EHTR to double hold time on read accesses. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 472 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank. 0 LBCTL is asserted upon access to the current memory bank. 1 LBCTL is not asserted upon access to the current memory bank. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-18 Freescale Semiconductor...
Page 473: Upm Memory Address Register (Mar)
Table 10-10. MAR Field Descriptions Bits Name Description 0–31 Address that can be output to the address signals under control of the AMX bits in the UPM RAM word. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-19...
Page 474 UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode. 0 LUPWAIT is active high. 1 LUPWAIT is active low. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-20 Freescale Semiconductor...
Page 475 Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or 14–17 single-beat read pattern or when M x MR[OP] = 11 ( command) 0000 16 0001 1 0010 2 0011 3 1110 14 1111 15 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-21...
Page 476: Memory Refresh Timer Prescaler Register (Mrtpr)
10-10, contains data written to or read from the RAM array for UPM read or write commands. MDR also contains data written to or read from MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-22 Freescale Semiconductor...
Page 477: Special Operation Initiation Register (Lsor)
LSOR must not be rewritten before a pending special operation has been completed. The UPM and FCM have different indications of when such special operations are completed. The MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 478: Upm Refresh Timer (Lurt)
UPM. The qualified banks rotate their requests. Offset 0x0A0 Access: Read/Write LURT — Reset All zeros Figure 10-12. UPM Refresh Timer (LURT) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-24 Freescale Semiconductor...
Page 479: Transfer Error Status Register (Ltesr)
LTESR if they have been enabled in LTEDR. Offset 0x0B0 Access: w1c — — ATMW — — Reset All zeros — Reset All zeros Figure 10-13. Transfer Error Status Register (LTESR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-25...
Page 480 1 UPM Run pattern operation has completed, allowing software to continue processing of results. FCM command completion event 0 No FCM operation in progress, or operation pending. 1 FCM operation has completed, allowing software to continue processing of results. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-26 Freescale Semiconductor...
Page 481: Transfer Error Check Disable Register (Ltedr)
1 RAWA error checking is disabled. 10–11 — Reserved Chip select error checking disable. 0 Chip select error checking is enabled. 1 Chip select error checking is disabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-27...
Page 482: Transfer Error Interrupt Enable Register (Lteir)
1 FCM command time-out error reporting is enabled. PARI ECC error interrupt enable. 0 ECC error reporting is disabled. 1 ECC error reporting is enabled. 3–4 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-28 Freescale Semiconductor...
Page 483: Transfer Error Attributes Register (Lteatr)
Access: Read/Write 10 11 15 16 19 20 23 24 30 31 — — SRCID — Reset All zeros Figure 10-16. Transfer Error Attributes Register (LTEATR MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-29...
Page 484: Transfer Error Address Register (Ltear)
Transaction address for the error. For GPCM and UPM, holds the 32-bit address of the transaction resulting in an error. For FCM, this register is undefined. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-30 Freescale Semiconductor...
Page 485: Transfer Error Ecc Register (Lteccr)
The local bus configuration register (LBCR) is shown in Figure 10-19. Offset 0x0D0 Access: Read/Write LDIS — BCTLC — Reset — BMTPS Reset All zeros Figure 10-19. Local Bus Configuration Register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-31...
Page 486 1001 PS = 4096 1010 PS = 8192 1011 PS = 16,384 1100 PS = 32,768 1101 PS = 65,536 1110 PS = 131,072 1111 PS = 262,144 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-32 Freescale Semiconductor...
Page 487: Clock Ratio Register (Lcrr)
Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. 00000–00001 Reserved 00010 2 00011 Reserved 00100 4 00101–00111 Reserved 01000 8 01001–11111 Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-33...
Page 488: Flash Mode Register (Fmr)
FCM buffer RAM, which maps only the 4 Kbytes of NAND Flash main data region comprising the boot block. Any access to the buffer RAM is delayed until the entire boot block has been loaded. 21–22 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-34 Freescale Semiconductor...
Page 489: Flash Instruction Register (Fir)
FBCR while an operation is in progress—or eLBC will behave unpredictably—but software can freely modify the contents of any currently unused FCM RAM buffer in preparation for the next operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 490: Flash Command Register (Fcr)
NAND Flash device. Offset 0x0E8 Access: Read/Write 15 16 23 24 CMD0 CMD1 CMD2 CMD3 Reset All zeros Figure 10-23. Flash Command Register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-36 Freescale Semiconductor...
Page 491: Flash Block Address Register (Fbar)
NAND Flash page in both the external NAND Flash device and FCM buffer RAM. Offset 0x0F0 Access: Read/Write — Reset All zeros Figure 10-25. Flash Page Address Register, Small Page Device (ORx[PGS] = 0) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-37...
Page 492 The LSB of PI indexes one of the two 4 Kbyte buffers in the FCM buffer RAM as follows: 0 The page is transferred to/from FCM buffer 0, address offsets 0x0000–0x0FFF 1 The page is transferred to/from FCM buffer 1, address offsets 0x1000–0x1FFF MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-38 Freescale Semiconductor...
Page 493: Flash Byte Count Register (Fbcr)
It can be used for verify after write feature in software. Note that the valid bit sets before the command completion event and hence the correct ECC could be read before actual completion of writes/reads. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-39...
Page 494 These patterns define how the external control signals behave during a read, write, burst-read, or burst-write access. Refresh timers are also available to periodically initiate user-defined refresh patterns. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-40 Freescale Semiconductor...
Page 495: Basic Architecture
BRn and ORn for that bank are used to control the memory access. If a match is found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank 0 has priority over bank 1). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-41...
Page 496: External Address Latch Enable Signal (Lale)
To illustrate how a large transaction is handled by the eLBC, Figure 10-30 shows eLBC signals for the GPCM performing a 32-byte write starting at address 0x5420. Note that during each of the 32 assertions MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-42 Freescale Semiconductor...
Page 497: Data Transfer Acknowledge (Ta)
TA whenever data read and write instructions are executed out of register FIR; a UPM generates TA only when a UPM pattern has the UTA RAM word bit set. Figure 10-31 shows LALE, TA (internal), and LCSn. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-43...
Page 498: Data Buffer Control (Lbctl)
During the reservation period, no other device can be granted access to the atomic bank. The reservation is released when the device that created it accesses the same bank with a write MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-44...
Page 499: Bus Monitor
Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 500: Gpcm Read Signal Timing
TA. LOE and LCSn negate high simultaneously, in some cases before the end of the read access to provide additional hold time for the external memory. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-46...
Page 501 (1½+SCY) ½ 1½ + SCY 3 + SCY 2 + SCY 3 + SCY 1 + SCY 3 + SCY 1 + SCY 4 + SCY MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-47...
Page 502: Gpcm Write Signal Timing
Write data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high before the end of the write access to provide additional hold time for the external memory. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-48...
Page 503 2 + SCY ¼ 1½ + SCY 1¾ + SCY (½) (1½+SCY) ½ 1¼ + SCY 1¾ + SCY (1+SCY) (1½+SCY) 2 + SCY ¼ 2 + SCY MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-49...
Page 504: Chip-Select Assertion Timing
Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1. • Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1 and ORn[TRLX] = 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-50 Freescale Semiconductor...
Page 505: Programmable Wait State Configuration
When this attribute is asserted, the strobe is negated one quarter of a clock before the normal case provided that LCRR[CLDIV] = 4 or 8. For example, when ACS = 00 and MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 506: Relaxed Timing
The effect of LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-52...
Page 507 Figure 10-38. GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-53...
Page 508 LWE n Figure 10-40. GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-54 Freescale Semiconductor...
Page 509: Output Enable (Loe) Timing
Latched Address 1 Latched Address 2 LCS n LCS y LBCTL Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-55...
Page 510: External Access Termination (Lgta)
The user selects whether transfer acknowledge is generated internally or externally (LGTA) by programming ORn[SETA]. Asserting LGTA always terminates an access, even if ORn[SETA] = 0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-56 Freescale Semiconductor...
Page 511: Gpcm Boot Chip-Select Operation
LCS0 operates this way until the first write to OR0 and it can be used as any other chip-select register after the preferred address range is loaded into BR0. After the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 512: Flash Control Machine (Fcm)
4.7-KΩ resistor. On system reset, a global (boot) 1. Note bit numbering reversal: LAD[0] (msb) connects to Flash IO[7], while LAD[7] (lsb) connects to IO[0]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-58...
Page 513 FCM NAND Flash EEPROM 4.7KΩ Mode LFRB RDY/BSY LFWP LALE N.C. N.C. LAD[0:7] IO[7:0] LAD[8:15] N.C. Figure 10-44. Local Bus to 8-Bit FCM Device Interface MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-59...
Page 514: Fcm Buffer Ram
External eLBC signals, such as LALE and LCSn, will not assert upon accesses to the buffer RAM. The FCM buffer RAM is logically divided into two or more buffers, MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-60...
Page 515: Buffer Layout And Page Mapping For Small-Page Nand Flash Devices
However, for commands given a specific byte count in FBCR[BC], FPAR[MS] locates the starting address in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC banks control both MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 516: Buffer Layout And Page Mapping For Large-Page Nand Flash Devices
However, for commands given a specific byte count in FBCR[BC], FPAR[MS] locates the starting address in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-62...
Page 517: Error Correcting Codes And The Spare Region
The placement of ECC code words in relation to FMR[ECCM] is shown in Figure 10-49. For small-page devices, only a single 512-byte main region is ECC-protected. For large-page devices, there are four MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-63...
Page 518: Programming Fcm
MDR all reset to select AS0 at the start of the instruction sequence. A complete list of op-codes can be found in Section 10.3.1.18, “Flash Instruction Register (FIR).” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-64 Freescale Semiconductor...
Page 519: Fcm Command Instructions
The manufacturer’s datasheet should be consulted to determine values for programming into the FCR register, and whether a given command in the sequence is expected to initiate busy device behavior. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 520: Fcm No-Operation Instruction
(8-bit port size) of data into the next AS field of MDR. Reads beyond the fourth byte of MDR are discarded. The MDR read pointer is independent of the MDR write pointer used by UA and WS instructions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-66 Freescale Semiconductor...
Page 521: Fcm Data Write Instructions
Table 10-35. FCM Chip-Select to First Command Timing ORn[TRLX] ORn[CSCT] LCS n to First Command Delay 1 LCLK clock cycle 4 LCLK clock cycles 2 LCLK clock cycles 8 LCLK clock cycles MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-67...
Page 522: Fcm Command, Address, And Write Data Timing
2 × SCY 3 + 2 × SCY 8 × (2 + SCY) In the parameters, SCY refers to a delay of OR n [SCY] clock cycles. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-68 Freescale Semiconductor...
Page 523: Fcm Ready/Busy Timing
LFRB. This guards against observing LFRB before it has been properly driven low by the device, but does not preclude LFRB from MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 524: Fcm Read Data Timing
= Read data cycle time. = Write to read turnaround time. Figure 10-55. FCM Read Data Timing (for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-70 Freescale Semiconductor...
Page 525: Fcm Extended Read Hold Timing
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is the boot chip-select output; its operation differs from other external chip-select outputs after a system reset. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 526: Fcm Bank 0 Reset Initialization
Since OR0[AM] is initially cleared during reset, all CPU fetches to eLBC will access the FCM buffer RAM, which appears in the memory map as a 4-Kbyte RAM. No NAND Flash spare regions are mapped MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-72...
Page 527 512-byte region is verified and single-bit errors are corrected if possible. If FCM is unable to correct ECC errors, eLBC halts the boot process and signals an unrecoverable error by asserting the hreset_req signal. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-73...
Page 528: User-Programmable Machines (Upms)
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh • A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an exception sequence MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-74 Freescale Semiconductor...
Page 529: Upm Requests
Table 10-39. UPM Routines Start Addresses UPM Routine Routine Start Address Read single-beat (RSS) 0x00 Read burst (RBS) 0x08 Write single-beat (WSS) 0x18 Write burst (WBS) 0x20 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-75...
Page 530: Memory Access Requests
MxMR[RFEN] bits are set. In this scenario, more than one chip select may assert at the same time, as refresh pattern runs for all banks assigned to UPM with RFEN bit set. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-76...
Page 531: Software Requests—Run Command
MxMR/MDR registers should not be updated while dummy read/write access is still in progress. If the MxMR[MAD] is incremented then the previous dummy transaction is already completed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-77...
Page 532: Upm Programming Example (Two Sequential Writes To The Ram Array)
8. Read MDR to ensure that the MDR has already been updated with the desired pattern. 9. Perform a dummy write transaction. 10. Read/check MxMR[MAD]. If incremented, the previous dummy write transaction is completed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-78 Freescale Semiconductor...
Page 533: Upm Programming Example (Two Sequential Reads From The Ram Array)
T1–T4, define four quarters of the bus clock cycle. Because T2 and T4 are inactive when LCRR[CLKDIV] = 2, UPM ignores signal timing programmed for assertion in either of these phases in the case LCRR[CLKDIV] = 2. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-79...
Page 534: Ram Array
The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies timing for external signals controlled by the UPM. Figure 10-37 shows the RAM word fields. When MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-80 Freescale Semiconductor...
Page 535 General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases 1 and 2 (first half phase). 00 Value defined by M x MR[G0CL] 01 Reserved 10 0 11 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-81...
Page 536 Redo current RAM word. Defines the number of times to execute the current RAM word. 00 Once (normal operation) 01 Twice 10 Three times 11 Four times MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-82 Freescale Semiconductor...
Page 537 1 The disable timer for the current bank is activated preventing a new access to the same bank (when controlled by the UPMs) until the disable timer expires. For example, precharge time. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 538 LCSn for that bank with timing as specified in the UPM RAM word CSTn fields. The selected UPM affects only the assertion and negation of the appropriate LCSn signal. The state of the selected LCSn MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-84...
Page 539 UPM affects the assertion and negation of the appropriate LBS[0:1] signal. The timing of both byte-select signals is specified in the RAM word. However, LBS[0:1] are also controlled by the port size of the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 540: Loop Control (Loop)
Loops can be executed sequentially but cannot be nested. Also, special care must be taken: • LAST and LOOP must not be set together. • Loop start word should not have an AMX change with regard to the previous word. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-86 Freescale Semiconductor...
Page 541: Repeat Execution Of Current Ram Word (Redo)
(NA) bit of the RAM word is used to increment the current address. The effect of NA = 1 is visible only when AMX = 00 chooses the column address. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 542 ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word during the LALE phase. NOTE AMX must not change values in any RAM word which begins a loop. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-88 Freescale Semiconductor...
Page 543: Data Valid And Data Sample Control (Uta)
The WAEN bit is ignored if LAST = 1 in the same RAM word. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 544 ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to any existing bus turnaround cycle. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-90 Freescale Semiconductor...
Page 545: Interfacing To Peripherals In Different Address Modes
LA[0:25], in which case addresses driven onto LAD during address phases are simply ignored. The connection is illustrated in Figure 10-70. In non-multiplexed mode, the waveforms MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-91...
Page 546: Peripheral Hierarchy On The Local Bus For High Bus Speeds
LA n LAD n Latch LALE Slower Memories LBCTL Peripherals Muxed Address/Data Unmuxed Address Buffered Data Figure 10-71. Local Bus Peripheral Hierarchy for High Bus Speeds MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-92 Freescale Semiconductor...
Page 547: Gpcm Timings
Read-modify-write cycle for parity protected memory banks • UPM cycles with additional address phases The bus does not change direction for the following cases so they need no special attention: MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-93...
Page 548: Address Phase After Previous Read
The eLBC supports 8- and 16-bit data port sizes. However, the bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on LAD[0–15], and MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-94...
Page 549 Port Size/LAD Data Bus Assignments Address Transfer State 16-Bit 8-Bit Size 3 lsbs 0–7 8–15 16–23 24–31 0–7 8–15 16–23 24–31 Byte — — — — — — — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-95...
Page 550: Command Sequence Examples For Nand Flash Eeprom
Table 10-44. FCM Register Settings for Soft Reset (OR n [PGS] = 1) Register Initial Contents Description 0xFF00_0000 CMD0 = 0xFF = reset command; other commands unused FBAR — Unused FPAR — Unused FBCR — Unused MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-96 Freescale Semiconductor...
Page 551: Nand Flash Read Status Command Sequence Example
Table 10-46. FCM Register Settings for ID Read (OR n [PGS] = 1) Register Initial Contents Description 0x9000_0000 CMD0 = 0x90 = read ID command; other commands unused FBAR — Unused FPAR — Unused FBCR — Unused MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-97...
Page 552: Nand Flash Page Read Command Sequence Example
10-48. This sequence does not require use of the shared FCM buffer RAM, but returns with the erase status in MDR[AS0]. The sequence is initiated by writing FMR[OP] = 11, and issuing a special MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-98...
Page 553: Nand Flash Program Command Sequence Example
NAND Flash device might already be driving it, contention will occur. In case OP5 and OP6 operations are skipped, it may also MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 554: Interfacing To Fast-Page Mode Dram Using Upm
Here, LGPL1 is programmed to drive R/W of the DRAM, although any LGPLn signal may be used for this purpose. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-100...
Page 555 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS + 1 RSS + 1 RSS + 2 Figure 10-75. Single-Beat Read Access to FPM DRAM MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-101...
Page 556 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS + 1 WSS + 1 WSS + 2 Figure 10-76. Single-Beat Write Access to FPM DRAM MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-102 Freescale Semiconductor...
Page 557 Bit 30 last Bit 31 RBS + 1 RBS + 2 RBS + 3 Figure 10-77. Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 10-103...
Page 558 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS + 1 PTS + 2 Figure 10-78. Refresh Cycle (CBR) to FPM DRAM MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-104 Freescale Semiconductor...
Page 559: Interfacing To Zbt Sram Using Upm
The same interfacing is used for pipelined and flow-through versions of ZBT SRAMs. However different UPM patterns must be generated for those cases. As ZBT SRAMs are MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 560 (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-106...
Page 561 RAM word, then the eLBC may not be able to sample the correct data during reads. Therefore OE must be asserted earlier than TA. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 562 Enhanced Local Bus Controller MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 10-108 Freescale Semiconductor...
Page 563: Sequencer Overview
I/O sequencer (IOS). Configuration Regs. I/F Configuration Regs. Power Management Buffer Pool I/O Sequencer (IOS) Figure 11-1. I/O Sequencer Block Diagram MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 11-1...
Page 564: Sequencer Features
POTAR5—PCI outbound translation address register 5 All zeros 11.4.1/11-3 0x80 POBAR5—PCI outbound base address register 5 All zeros 11.4.2/11-3 0x88 POCMR5—PCI outbound comparison mask register 5 All zeros 11.4.3/11-4 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 11-2 Freescale Semiconductor...
Page 565: Sequencer Register Descriptions
POBARn register fields. Offset 0x08, 0x20, 0x38, Access: Read/Write 0x50, 0x68, 0x80 11 12 — Reset All zeros Figure 11-3. PCI Outbound Base Address Registers (POBAR n ) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 11-3...
Page 566 I/O space. Determines whether the window is mapped to the PCI memory space or PCI I/O space. 0 Memory space 1 I/O space 2–11 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 11-4 Freescale Semiconductor...
Page 567: Power Management Control Register (Pmcr)
0 Logic is active. 1 Logic is idle. There are no outstanding transactions in the IOS, the DMA, or the PCI port. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 11-5...
Page 568: Discard Timer Control Register (Dtcr)
Although the ports use a similar interface, the I/O sequencer is not actually symmetrical. The transaction forwarding from each source is explained in the following sections. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 11-6 Freescale Semiconductor...
Page 569: Transactions From The Coherency System Bus (Csb) Port
Transactions to these address ranges are issued on the PCI bus with a translated address. The translation addresses are defined in the associated PCI outbound translation address registers (POTARs). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 570: Transaction Ordering
PCI port and were posted before the read data arrives from the PCI. • The IOS can always accept a write from the PCI port without forcing the PCI port to first accept a read. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 11-8 Freescale Semiconductor...
Page 571: Dma Features
Message and doorbell registers for inter-processor communication • DMA controller — Four DMA channels — Concurrent execution across multiple channels with programmable bandwidth control — Misaligned transfer capability MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-1...
Page 572: Dma Memory Map/Register Definition
DMASR2—DMA 2 status register All zeros 12.3.8.2/12-11 0x0_8208 DMACDAR2—DMA 2 current descriptor address register All zeros 12.3.8.3/12-12 0x0_8210 DMASAR2—DMA 2 source address register All zeros 12.3.8.4/12-13 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-2 Freescale Semiconductor...
Page 573: Dma Register Descriptions
PCI bus. Figure 12-2 shows the OMISR fields. Offset 0x030 Access: Mixed OM1I OM0I — — Reset All zeros Figure 12-2. Outbound Message Interrupt Status Register (OMISR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-3...
Page 574: Outbound Message Interrupt Mask Register (Omimr)
Table 12-3. OMIMR Field Descriptions Bits Name Description 31–4 — Reserved ODIM Outbound doorbell interrupt mask. 0 Outbound doorbell interrupt is allowed 1 Outbound doorbell interrupt is masked — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-4 Freescale Semiconductor...
Page 575: Inbound Message Registers (Imr0–Imr)
Table 12-5. OMR0 and OMR1 Field Descriptions Bits Name Description 31–0 OMSG n Outbound message n . Contains generic data to be passed between the local processor and external hosts. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-5...
Page 576: Doorbell Registers
Write 1 from the PCI bus to clear. Writing 0 has no effect. (Writing a bit in this register from the CSB causes an interrupt (PCI_INTA) to be generated.) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-6 Freescale Semiconductor...
Page 577: Inbound Doorbell Register (Idr)
Figure 12-8 shows the IMISR fields. Offset 0x080 Access: User Mixed MCI IDI IM1I — — Reset All zeros Figure 12-8. Inbound Message Interrupt Status Register (IMISR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-7...
Page 578: Inbound Message Interrupt Mask Register (Imimr)
1 Machine check interrupt is masked. IMISR[MC1] is cleared IDIM Inbound doorbell interrupt mask. 0 Inbound doorbell interrupt is allowed 1 Inbound doorbell interrupt is masked. IMISR[IDI] is cleared. — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-8 Freescale Semiconductor...
Page 579: Dma Registers
DMA channels. The BWC values are listed as follows: 000 1 cache line 001 2 cache lines 010 4 cache lines 011 8 cache lines 100 16 cache lines Others Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-9...
Page 580 DMA transfer. End-of-transfer is defined as the end of a direct mode transfer or in chaining mode, as the end of the transfer of the last segment of a chain. 0 No EOT interrupt is generated 1 EOT interrupt is generated 6–4 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-10 Freescale Semiconductor...
Page 581 Channel busy. This bit indicates whether the channel is busy. It is cleared as a result of any of the following conditions: an error or completion of the DMA transfer. 0 No DMA transfer is currently in progress 1 A DMA transfer is currently in progress MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-11...
Page 582 End-of-segment interrupt enable 0 No end-of-segment interrupt is generated. 1 An interrupt is generated when the current DMA transfer for the current descriptor is finished. 2–0 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-12 Freescale Semiconductor...
Page 583 Table 12-14 describes the DMADARn register. Table 12-14. DMASAR n Field Descriptions Bits Name Description 31–0 Destination address of DMA transfer.Updated after each DMA write operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-13...
Page 584 NEOSIE Next end-of-segment interrupt enable. 0 No end-of-segment interrupt is generated. 1 An interrupt is generated when the DMA transfer for the next descriptor is finished. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-14 Freescale Semiconductor...
Page 585: Dma General Status Register (Dmagsr)
The interrupt to the local processor is cleared by writing 1 to the appropriate IMISR bit. The interrupt to PCI (PCI_INTA) is cleared by writing 1 to the appropriate OMISR bit. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 586: Doorbell Registers (Idr And Odr)
Direct mode, in direct mode, the DMA controller does not read a chain of descriptors from memory but instead uses the current parameters in the DMA registers to start a DMA transfer. The DMA MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-16...
Page 587: Dma Coherency
DMA current descriptor address register (DMACDARn) and the DMA next descriptor address register (DMANDARn) that allows software to control when the cache is snooped on a per segment basis. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-17...
Page 588: Halt And Error Conditions
DMA transfer with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain until reaching the last descriptor (with its EOTD bit set). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-18 Freescale Semiconductor...
Page 589: Descriptor In Big-Endian Mode
If segment descriptors are written to memory located in the CSB, they should be treated like they are translated from big-endian to little-endian mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 590: Descriptor In Little-Endian Mode
3. Initialize DMAMRn[CTM]) to indicate direct mode. Other control parameters in the mode register can also be initialized here if necessary. 4. First clear then set the DMAMRn[CS] to start the DMA transfer. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-20 Freescale Semiconductor...
Page 591: Initialization Steps In Chaining Mode
4. Initialize the DMAMRn[CTM] to indicate chaining mode. Other control parameters in the mode register can also be initialized here if necessary. 5. First clear then set the DMAMRn[CS] to start the DMA transfer. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 12-21...
Page 592 DMA/Messaging Unit MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 12-22 Freescale Semiconductor...
Page 593: Pci Introduction
The PCI controller acts as a bridge between the PCI interface and the CSB. The I/O sequencer buffers the data. Figure 13-1 is a high-level block diagram of the PCI controller. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-1...
Page 594 Systems must not rely on inbound reads to ensure all pending outbound writes have completed. For example, consider the case where a core writes data to a PCI device and then updates a flag in the local MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-2...
Page 595: Pci Features
When the device powers up in agent mode, it acknowledges inbound configuration accesses. Note that in PCI agent mode, the PCI controller ignores all PCI memory accesses except those to the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 596: Pci Arbiter Configuration
PCI system error High impedance Required PCI_STOP PCI stop High impedance Required PCI_TRDY PCI target ready High impedance Required PCI_PME PCI PME assertion request High impedance Required MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-4 Freescale Semiconductor...
Page 597 State Asserted—The PCI interface signals use the 66-MHz PCI AC timing parameters. Meaning Negated—The PCI interface signals use the 33-MHz PCI AC timing parameters. Timing Assertion/Negation—Constant MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-5...
Page 598 Asserted—Some PCI agents (other than this PCI controller) have decoded its address as Meaning the target of the current access. Negated—No PCI agent has been selected. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-6 Freescale Semiconductor...
Page 599 Negated—The PCI controller is not being selected as a target of configuration read or write transactions. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-7...
Page 600 Negated—Even parity driven by another PCI master or the PCI target during address and data phases. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-8 Freescale Semiconductor...
Page 601 Asserted—An agent n is requesting control of the PCI bus to perform a transaction. State Meaning Negated—An agent n does not require use of the PCI bus. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-9...
Page 602 Asserted—A target is requesting that this PCI controller, as the initiator, stop the current Meaning transaction. Negated—The current transaction can continue. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-10 Freescale Semiconductor...
Page 603: Pci Memory Map/Register Definitions
PCI Configuration Access Registers—Block Base Address 0x0_8300 0x00 PCI_CONFIG_ADDRESS All zeros 13.3.1.1/13-13 0x04 PCI_CONFIG_DATA All zeros 13.3.1.2/13-14 0x08 PCI_INT_ACK 13.3.1.3/13-15 0x80 PCIPMR0—PCI power management register 0 0x7E4B_0001 13.3.3.27/13-41 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-11...
Page 604 PCI inbound translation address register 0 (PITAR0) All zeros 13.3.2.11/13-22 0x6C Reserved — — — 0x70 PCI inbound base address register 0 (PIBAR0) All zeros 13.3.2.12/13-23 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-12 Freescale Semiconductor...
Page 605: Pci Configuration Access Registers
CONFIG_DATA when the EN bit is 0. 1 A configuration transaction will be generated by accessing the CONFIG_DATA register if BN and DN are not both zero. 30–24 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-13...
Page 606 13.3.1.2 PCI_CONFIG_DATA An access to PCI_CONFIG_DATA usually generates a PCI configuration transaction if PCI_CONFIG_ADDRESS[EN] is set. There are some exceptions contained in the description of PCI_CONFIG_ADDRESS[EN]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-14 Freescale Semiconductor...
Page 607: Pci Interrupt Acknowledge Register (Pci_Int_Ack)
PCI_ESR fields. Offset 0x00 Access: w1c R MERR APAR PCISERR MPERR TPERR NORSP TABT — — Reset All zeros Figure 13-5. PCI Error Status Register (PCI_ESR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-15...
Page 608: Pci Error Capture Disable Register (Pci_Ecdr)
PCI_ECDR fields. Offset 0x04 Access: Read/Write — APAR PCISERR MPERR TPERR NORSP TABT — Reset All zeros Figure 13-6. PCI Error Capture Disable Register (PCI_ECDR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-16 Freescale Semiconductor...
Page 609: Pci Error Enable Register (Pci_Eer)
Target parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1. NORSP No response. Generate an interrupt when the corresponding bit of the PCI_ESR is 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-17...
Page 610: Pci Error Attributes Capture Register (Pci_Eatcr)
0011 4th beat 0100 5th beat 0101 6th beat 0110 7th beat 0111 8th beat 1000 9th beat or beyond (transaction larger than one cache line) Others Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-18 Freescale Semiconductor...
Page 611: Pci Error Address Capture Register (Pci_Eacr)
Table 13-12. PCI_EACR Field Description Bits Name Description 0–31 PCI_EA PCI error address. Contains the low portion of the address associated with the first detected error. Read only. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-19...
Page 612: Pci Error Extended Address Capture Register (Pci_Eeacr)
PCI_GCR contains fields for controlling the behavior of the internal arbiter, the state of the bus signals, and the PCI reset signal for host mode. Figure 13-12 shows the PCI_GCR fields. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-20 Freescale Semiconductor...
Page 613: Pci Error Control Register (Pci_Ecr)
PCI_ECR fields. Offset 0x24 Access: Read/Write — APAR PCISERR MPERR TPERR NORSP TABT — Reset All zeros Figure 13-13. PCI Error Control Register (PCI_ECR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-21...
Page 614: Pci General Status Register (Pci_Gsr)
Chapter 11, “Sequencer”). Inbound and outbound windows for the same bus should not overlap. Therefore, situations where an inbound window translation points back into an MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-22 Freescale Semiconductor...
Page 615 43–12 of a 64-bit address. In PIBAR0, the upper 12 bits are reserved because only a 32-bit address is supported. The specified address must be aligned to the window size, as defined by PIWAR n [IWS]. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-23...
Page 616 1 Address translation is enabled for this window. PCI addresses that match the definition of the window will be recognized by the PCI controller and translated to the local memory space. — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-24 Freescale Semiconductor...
Page 617: Pci Configuration Space Registers
PCI configuration registers that are mapped in PCI configuration space. Some fields are common to registers in both spaces to ensure consistency. These fields are discussed in the register definitions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-25...
Page 618 Maximum latency configuration register PCI function configuration register PCI arbiter control register (PCIACR) Hot swap register block PCI power management register 0 PCI power management register 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-26 Freescale Semiconductor...
Page 619: Vendor Id Configuration Register
Table 13-23. Vendor ID Configuration Register Field Descriptions Bits Name Description 15–0 Vendor ID. The read-only value 0x1957 specifies Freescale Semiconductor as the manufacturer of the device. 13.3.3.2 Device ID Configuration Register Figure 13-20 shows the device ID fields. This is a read only register.
Page 620: Pci Command Configuration Register
0 The PCI controller does not respond to Memory Space accesses. 1 The PCI controller as a target responds to Memory Space accesses. I/O space. Hard-wired to 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-28 Freescale Semiconductor...
Page 621: Pci Status Configuration Register
Interrupt status. Contains the status of the device interrupt. The value of this bit is not affected by the INTD bit of the PCI command configuration register. 2–0 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-29...
Page 622: Revision Id Configuration Register
Table 13-28. Standard Programming Interface Configuration Register Field Descriptions Bits Name Description 7–0 Programming interface. This field is hard-wired to 0x00. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-30 Freescale Semiconductor...
Page 623: Subclass Code Configuration Register
Table 13-30. Class Code Configuration Register Field Descriptions Bits Name Description 7–0 Base class code. This field is hard-wired to 0x0B, indicating a processor. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-31...
Page 624: Cache Line Size Configuration Register
Refer to the PCI 2.3 specification for the rules by which the PCI controller completes transactions when the timer has expired. 2–0 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-32 Freescale Semiconductor...
Page 625: Header Type Configuration Register
Base address. Defines the base address for the internal (on-chip) memory-mapped register space. The size of this space is 1 Mbytes. 19–4 — Reserved Prefetchable. Hard-wired to 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-33...
Page 626: Gpl Base Address Register
IWS field. For read operations, these masked bits always return zeros. Figure 13-33 shows the GPL base address register 1–2 fields. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-34 Freescale Semiconductor...
Page 627 Table 13-36. GPL Extended Base Address Registers 1–2 Field Descriptions Bits Name Description 31–0 Extended base address. Defines the high portion of the base address for the inbound window. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-35...
Page 628: Subsystem Vendor Id Configuration Register
The capabilities pointer register specifies the byte offset in the PCI configuration space that contains the first item in the capabilities list. Figure 13-37 shows the capabilities pointer configuration register fields. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-36 Freescale Semiconductor...
Page 629: Interrupt Line Configuration Register
Offset 0x3D Interrupt Pin Reset Figure 13-39. Interrupt Pin Register 13.3.3.22 Minimum Grant Configuration Register Figure 13-40 shows the minimum grant configuration register fields. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-37...
Page 630: Maximum Latency Configuration Register
1 Any inbound PCI access to the PCI configuration space is retried. SeeSection 4.3.1.1, “Reset Configuration Word Source,” for more information on reset configuration. 3–4 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-38 Freescale Semiconductor...
Page 631: Pci Arbiter Control Register (Pciacr)
0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI clock periods after the bus becomes idle or its request is subsequently ignored. 1 No requests are ignored. 11–7 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-39...
Page 632: Hot Swap Register Block
Next pointer—hardwired to 0x80 to point to the address of the power management capability in the PCI controller. 7–0 CAP_ID Capability ID for hot swap (hardwired to 0x06) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-40 Freescale Semiconductor...
Page 633: Pci Power Management Register 0 (Pcipmr)
1 The PCI controller supports the D1 power management state. 24–22 Aux_Current Reports the 3.3 Vaux auxiliary current requirements Device specific initialization. Indicates whether special initialization of this PCI controller is required. — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-41...
Page 634: Pci Power Management Register 1 (Pcipmr)
1 Enable the bus power/clock control policies defined in section 4.7.1 of the PCI Bus Power Management Interface Specification Revision 1.2 Note: This bit field is not implemented, only required for all PCI-to-PCI Bridge MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-42 Freescale Semiconductor...
Page 635: Pci Bus Arbitration
Arbitration for the bus occurs during the previous access so that no PCI bus cycles are consumed waiting for arbitration (except when the bus is idle). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-43...
Page 636: Bus Parking
An arbitration example with three masters in the high priority group and two in the low priority group is shown in Figure 13-47. Noting that one position in the high priority group is actually a place-holder for MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-44 Freescale Semiconductor...
Page 637: Broken Master Lock-Out
PCI controller completes one more data phase and relinquishes the bus. The master latency timer can be disabled if needed (see Section 13.3.3.24, “PCI Function Configuration Register,” for more information). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-45...
Page 638: Bus Commands
Indicates that the initiator will transfer an entire cache line of data, and if 0b1111 invalidate PCI has any cacheable memory, this line needs to be invalidated. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-46 Freescale Semiconductor...
Page 639: Pci Protocol Fundamentals
IDSEL is asserted, and AD[1:0] are 0b00; otherwise, the agent ignores the current transaction. The PCI controller determines MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 640: Device Selection
(An idle cycle in PCI is when both PCI_FRAME and PCI_IRDY are negated). Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is not valid. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-48 Freescale Semiconductor...
Page 641: Bus Transactions
PCI_CLK PCI_AD[31:0] ADDR DATA PCI_C/BE[3:0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 13-48. Single Beat Read Example MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-49...
Page 642 Figure 13-50 shows an example of a single-beat write transaction. PCI_CLK PCI_AD[31:0] ADDR DATA PCI_C/BE[3:0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 13-50. Single Beat Write Example MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-50 Freescale Semiconductor...
Page 643: Transaction Termination
However, if PCI_TRDY is negated when PCI_STOP is asserted, no more data is transferred, and the initiator therefore does not have to wait for a final data transfer (see the retry diagram in Figure 13-50). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-51...
Page 644 This can occur because no buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-52...
Page 645: Other Bus Operations
PCI_DEVSEL in the previous cycle, it delays the assertion of PCI_DEVSEL and PCI_TRDY for one cycle to allow the other target to get off the bus. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 646: Dual Address Cycles
If the enable bit is set and the device number is not equal to all ones, a configuration cycle translation is performed. When the device number field is equal to all ones, it has a special meaning (see Section 13.4.4.6, “Special Cycle Command,” for more information). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-54 Freescale Semiconductor...
Page 647: Agent Mode Configuration Access
A special cycle command is like any other bus command in that it has an address phase and a data phase. The address phase starts like all other commands with the assertion of PCI_FRAME and completes when MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 648: Interrupt Acknowledge
The interrupt vector must be returned when PCI_TRDY is asserted. An interrupt acknowledge transaction can also be issued on the PCI bus by reading from the PCI_INT_ACK register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-56 Freescale Semiconductor...
Page 649: Error Functions
When acting as an initiator during a read transaction or as a target involved in a write to system memory the PCI controller asserts PCI_PERR. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 650 If the PCI controller detects a parity error on a read from PCI, the PCI controller aborts the transaction internally and continues the transfer on the PCI bus, allowing the target to abort/disconnect if desired. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-58 Freescale Semiconductor...
Page 651: Pci Inbound Address Translation
The translation windows are disabled after reset, that is, after reset, the PCI controller does not acknowledge externally mastered transactions on the PCI bus by asserting PCI_DEVSEL until the inbound translation windows are enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-59...
Page 652: Compactpci Hot Swap Specification Support
Big endian Little endian source bus destination bus Byte lane Address lsbs Data Significance Figure 13-55. Address Invariant Byte Ordering—4 bytes Outbound MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-60 Freescale Semiconductor...
Page 653 CFG_DATA, including the those targeting the internal PCI configuration registers, use the address invariance policy as shown in Figure 13-59. Therefore, software must access CFG_DATA with MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 13-61...
Page 654: Initialization Sequence For Host Mode
1. Optionally initialize subsystem vendor ID/device ID a) Initialize PCI inbound window size in PIWAR[1:3] desired window size b) Unlock configuration lock in PCI function configuration register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 13-62 Freescale Semiconductor...
Page 655 The SEC 2.2 is designed to off-load computationally intensive security functions, such as authentication, and bulk encryption from the processor core of the MPC8313E. It is optimized to process all the algorithms associated with IPSec, SSL/TLS, iSCSI, SRTP, and 802.11i. The SEC 2.2 is derived from integrated security cores found in other members of the PowerQUICC family, including SEC 1.0, the version...
Page 656: Sec 2.2 Architecture Overview
Core DUART DDR-1/DDR-2 eLBC IPIC Security GPIO 16K-I 16K-D Controller Timers System Bus I/O Sequencer (IOS) Figure 14-1. SEC Connected to MPC8313E System Bus MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-2 Freescale Semiconductor...
Page 657 Some descriptor types perform multiple functions to facilitate particular protocols. A descriptor is diagrammed in Table 14-1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-3...
Page 658 ECB mode, the contents of the IV field do not affect the result of the DES computation. Therefore, when processing descriptors, the channel skips any pointer that has an associated length of zero. For more information, refer to Section 14.3, “Descriptor Overview.” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-4 Freescale Semiconductor...
Page 659: Execution Units (Eus)
• The MD5 generates a 128-bit hash, and the algorithm is specified in RFC 1321. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-5...
Page 660 It can signal done through an interrupt or by a writeback of the descriptor header after processing a descriptor. Two values cam be written back: the first is identical to that of the header, with the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-6...
Page 661: Sec Controller
The SEC controller manages on-chip resources, including the individual execution units (EUs), FIFOs, the master/slave interface to the MPC8313E system bus, and the internal buses that connect all the various modules. The controller receives service requests from the master/slave interface and from the channel, and schedules the required activities.
Page 662: Host-Controlled Access
0x3_4000–0x3_4FFF AESU AES execution unit Section 14.4.3, “Advanced Encryption Standard Execution Unit (AESU)” 0x3_6000–0x3_6FFF MDEU Message digest execution unit Section 14.4.2, “Message Digest Execution Unit (MDEU)” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-8 Freescale Semiconductor...
Page 663 DEUIV—DEU IV register 14.4.1.9/14-27 0x3_2400 DEUK1—DEU key 1 register 14.4.1.10/14-28 0x3_2408 DEUK2—DEU key 2 register 14.4.1.10/14-28 0x3_2410 DEUK3—DEU key 3 register 14.4.1.10/14-28 0x3_2800– DEU FIFO 14.4.1.11/14-28 0x3_2FFF MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-9...
Page 664: Descriptor Overview
‘descriptor’ containing all the information the SEC needs to perform the security operation. The host creates the descriptor in main memory, then writes a pointer to the descriptor into the fetch FIFO of the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-10...
Page 665: Descriptor Structure
‘Field’ rows of Figure 14-4, and described in Table 14-4. The SEC device drivers allow the host to create proper headers for each cryptographic operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-11...
Page 666 14-5), or both, depending upon the states of the CDIE (Channel Done Interrupt Enable) and CDWE (Channel Done Writeback Enable) bits in the channel configuration register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-12 Freescale Semiconductor...
Page 667: Selecting Execution Units—Eu_Sel0 And Eu_Sel
Table 14-6. EU_SEL0 and EU_SEL1 Values Value Selected EU (Binary) 0000 No EU selected 0010 0011 MDEU 0110 AESU Others Reserved 1111 Reserved for header writeback MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-13...
Page 668: Selecting Descriptor Type—Desc_Type
SRTP encryption and hashing 0011_1 — Reserved 0100_1 — Reserved 0101_1 — Reserved 0110_1 — Reserved 0111_1 — Reserved 1000_1 tls_ssl_block TLS/SSL generic block cipher 1001_1 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-14 Freescale Semiconductor...
Page 669: Descriptor Format: Pointer Dwords
On occasion, a descriptor field may not be applicable to the requested service. With seven pointer dwords, it is possible that not all these dwords will be required to specify the input and output parameters. (Some MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 670: Link Table Format
R (return) bit set. The R bit signifies the end of link table operations so that the channel returns to the descriptor for its next pointer (if any). A single link table entry is shown in Figure 14-6. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-16 Freescale Semiconductor...
Page 671 The last byte of the required parcel size (Extent3) must coincide with the last byte of a memory segment, or unpredictable results may occur. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 672: Descriptor Types
In FIFO Out FIFO Cipher IV Out Length outbound Auth & CIpher Cipher Only undefined undefined undefined In FIFO MAC Out undefined tls_ssl_ Extent Auth only block MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-18 Freescale Semiconductor...
Page 673: Execution Units
14.4.1.1 DEU Mode Register (DEUMR) The DEU mode register (DEUMR) contains three bits that are used to program DEU operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-19...
Page 674: Deu Key Size Register (Deuksr)
DES (K1 = K3) or 24 bytes (168 bits for 3-key triple DES) will generate an error. Triple DES always uses K1 to encrypt, K2 to decrypt, K3 to encrypt (any write to K1 duplicates that value into K3 in case 2-key 3DES is desired). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-20 Freescale Semiconductor...
Page 675: Deu Data Size Register (Deudsr)
DEUDSR is cleared when the DEU is reset or re-initialized. Field — Data Size (bits) Reset Addr DEU 0x3_2010 Figure 14-9. DEU Data Size Register (DEUDSR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-21...
Page 676: Deu Reset Control Register (Deurcr)
The RESET_DONE bit in the DEU status register (DEUSR) will indicate when this initialization routine is complete 0 Do not reset 1 Full DEU reset MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-22 Freescale Semiconductor...
Page 677: Deu Status Register (Deusr)
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating the EU is ready for operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 678: Deu Interrupt Status Register (Deuisr)
Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate for triple DES) was written to the DEU key size register 0 No error detected 1 Key size error MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-24 Freescale Semiconductor...
Page 679: Deu Interrupt Control Register (Deuicr)
If the corresponding bit is not set, then upon detection of an error, the DEUISR is updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt processing. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-25...
Page 680 Output FIFO error. The shared symmetric output FIFO was detected non-empty upon write of DEU data size register 0 Output FIFO non-empty error enabled 1 Output FIFO non-empty error disabled MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-26 Freescale Semiconductor...
Page 681: Deu End-Of-Message Register (Deuemr)
DEU. Reading this memory location while the module is processing data generates an error interrupt. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 682: Deu Fifos
The MDEUMR is cleared when the MDEU is reset or re-initialized. Setting a reserved mode bit will generate a data error. If the mode register is modified during processing, a context error is generated. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-28...
Page 683 0 Normal operation 1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should be 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-29...
Page 684 1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs do not match, send an error interrupt to the channel. The number of bytes to be compared is given by the ICV size register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-30 Freescale Semiconductor...
Page 685: Recommended Settings For Mdeumr
0 (on) To generate an HMAC for a message that is spread across a sequence of descriptors, the following mode register bit settings should be used: MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-31...
Page 686: Mdeu Key Size Register (Mdeuksr)
CONT bit of the MDEU mode register (MDEUMR) is high, the data size must be a multiple of the 512-bit block size (that is, bits 55–63 must be written as 0). Violating either of these conditions causes a data size error (DSE in the MDEUISR). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-32 Freescale Semiconductor...
Page 687: Mdeu Reset Control Register (Mdeurcr)
Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for the MDEU. All registers and internal state are returned to their defined reset state. 0 No reset 1 Full MDEU reset MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-33...
Page 688: Mdeu Status Register (Mdeusr)
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller interrupt status register (Section 14.6.4.3, “Interrupt Status Register (ISR)”). 0 MDEU is not signaling error 1 MDEU is signaling error MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-34 Freescale Semiconductor...
Page 689: Mdeu Interrupt Status Register (Mdeuisr)
MDEU. Early read error. The MDEU context was read before the MDEU completed the hashing operation. 0 No error detected 1 Early read error MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-35...
Page 690: Mdeu Interrupt Control Register (Mdeuicr)
Field — — IE ERE CE KSE DSE ME AE — — Reset 0x3000 Addr MDEU 0x3_6038 Figure 14-22. MDEU Interrupt Control Register (MDEUICR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-36 Freescale Semiconductor...
Page 691: Mdeu Icv Size Register
MDEU performs ICV comparison (see Section 14.4.2.1, “MDEU Mode Register (MDEUMR)”). The MDEU ICV size register is cleared when the MDEU is reset or re-initialized. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-37...
Page 692: Mdeu End-Of-Message Register (Mdeuemr)
After a power-on reset, all the MDEU context register values are cleared to 0. Figure 14-25 shows how the MDEU context registers are initialized if the INIT bit is set in the MDEU mode register. All registers are MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-38 Freescale Semiconductor...
Page 693: Mdeu Key Registers
14.4.2.12 MDEU Key Registers The MDEU maintains eight 64-bit registers for writing an HMAC key. The IPAD and OPAD operations are performed automatically on the key data when required. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-39...
Page 694: Mdeu Fifos
If the mode register is modified during processing, a context error will be generated. Field — — Reset Addr AESU 0x3_4000 Figure 14-26. AESU Mode Register (AESUMR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-40 Freescale Semiconductor...
Page 695 Note: This bit is ignored if CM is set to ‘11’ (CTR mode). Table 14-26. AES Cipher Modes Mode ECM (56–57) CM (61–62) CCM (without ICV comparison) CCM with ICV comparison MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-41...
Page 696: Aesu Key Size Register (Aesuksr)
AESUKSR is cleared when the AESU is reset or re-initialized. If a key size other than 16, 24, or 32 bytes is specified, an illegal key size error will be generated. If the key size register is modified during processing, a context error will be generated. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-42 Freescale Semiconductor...
Page 697: Aesu Data Size Register (Aesudsr)
14-29, allows three levels reset of just AESU, as defined by the three self-clearing bits. Field — Reset Addr AESU 0x3_4018 Figure 14-29. AESU Reset Control Register (AESURCR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-43...
Page 698: Aesu Status Register (Aesusr)
0–39 — Reserved 40–47 The number of dwords currently in the output FIFO 48–55 The number of dwords currently in the input FIFO 56–57 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-44 Freescale Semiconductor...
Page 699: Aesu Interrupt Status Register (Aesuisr)
Field — — ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU — Reset Addr AESU 0x3_4030 Figure 14-31. AESU Interrupt Status Register (AESUISR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-45...
Page 700 1 Input FIFO non-empty error Input FIFO underflow. The AESU input FIFO has been read while empty. 0 No error detected 1 Input FIFO has had underflow error MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-46 Freescale Semiconductor...
Page 701: Aesu Interrupt Control Register (Aesuicr)
1 Internal error disabled Early read error. The AESU IV register was read while the AESU was processing. 0 Early read error enabled 1 Early read error disabled MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-47...
Page 702: Aesu End-Of-Message Register (Aesuemr)
(always 128) will be processed. Writing to the AESUEMR causes the AESU to process the final block of a message, allowing it to signal DONE. A read of the AESUEMR will always return a zero value. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-48 Freescale Semiconductor...
Page 703: Aesu Context Registers
Must be written at start of new CCM decryption. Header size/MAC size is only used if AES-CCM processing is suspended and resumed. Figure 14-34. AESU Context Registers MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-49...
Page 704: Context For Cbc Mode
CCM context is such a way that the context can be fetched as a contiguous string into the context registers, prior to encryption/MAC generation or decryption/MAC validation. The context register contents for CCM mode is summarized in Figure 14-35 and further described below. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-50 Freescale Semiconductor...
Page 705 MIC written out to memory by the AESU is the full 128 bits. The host must only append the most-significant 64 bits to the frame as the MIC. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 706 Note that for both encrypt and decrypt operations, if the IEEE Std. 802.11 frame is being processed as a whole (not split across multiple descriptors), the ‘Initialize’ and ‘Final MAC’ bits should be set in the AESU mode register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-52 Freescale Semiconductor...
Page 707: Aesu Key Registers
Upon notification of completion of the EU reset sequence, initialize mode registers in the assigned • Initialize EUs and write to EU registers such as key size and text-data size. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-53...
Page 708 If the NT field is 1, done notification is only performed on descriptors in which the DN bit is set in the packet header (Table 14-4). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-54 Freescale Semiconductor...
Page 709: Channel Registers
Burst size—The SEC accesses long text-data parcels in main memory through bursts of programmable size: 0 Burst size is 64 bytes 1 Burst size is 128 bytes MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-55...
Page 710 DN (Done Notification) bit is set in the header word of the descriptor, then notify the host by asserting an interrupt. Refer to Section 14.5.2, “Channel Interrupts,” for complete description of channel interrupt operation. — Reserved, set to zero MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-56 Freescale Semiconductor...
Page 711: Crypto-Channel Pointer Status Register (Ccpsr)
STATE field. Note: CHN_State is documented for information only. The User will not typically care about the channel state machine. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-57...
Page 712 0 The assigned secondary EU reset done signal is inactive. 1 The assigned secondary EU reset done signal is active indicating its reset sequence has completed and it is ready to accept data. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-58 Freescale Semiconductor...
Page 713 Table 14-33. G_STATE and S_STATE Field Values Value Gather State Machine: GS_IDLE GS_LOAD_POINTER GS_LOAD_POINTER_DONE GS_LOAD_NEXT_POINTER GS_PROCESS_POINTER GS_TRANS_BLOCK GS_TRANS_BLOCK_DONE GS_TRANS_BYTES GS_TRANS_BYTES_DONE GS_INC_PAIR_PTR GS_UPDATE GS_DONE GS_ERROR GS_RELOAD GS_TRANS_INBOUND GS_TRANS_INBOUND_DONE MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-59...
Page 714 0x16 TRANS_REQUEST_WRITE_SNOOPIN 0x39 MAC_TO_CIPHER_DONE 0x17 DELAY_PRI_SEC_DONE 0x3A READ_PRI_STATUS 0x18 TRANS_REQUEST_WRITE 0x3C READ_SEC_STATUS 0x19 WRITE_KEY_SIZE Others Reserved 0x1B DELAY_PRI_DONE 0x1E WRITE_DATASIZE_SEC_SNOOPOUT 0x1F TRANS_REQUEST_READ_SNOOPOUT 0x20 DELAY_SEC_DONE 0x21 TRANS_REQUEST_READ MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-60 Freescale Semiconductor...
Page 715 Table 14-36. Crypto-Channel Pointer Status Register PAIR_PTR Field Values Value Error 0x00 Processing header or pointer dword 0 0x01 Processing pointer dword 1 0x02 Processing pointer dword 2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-61...
Page 716: Crypto-Channel Current Descriptor Pointer Register (Cdpr)
In typical operation, the host CPU will create a descriptor in memory containing all relevant mode and location information for the SEC, then ‘launch’ the SEC by writing the address of the descriptor to the fetch FIFO. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-62 Freescale Semiconductor...
Page 717: Descriptor Buffer (Db)
— Pointer2 Length3 Extent3 — Pointer3 Length4 Extent4 — Pointer4 Length5 Extent5 — Pointer5 Length6 Extent6 — Pointer6 Address Channel_1 0x3_1180–0x3_11BF Figure 14-40. Descriptor Buffer (DB) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-63...
Page 718: Channel Interrupts
The controller interfaces to the host through the master/slave bus interface and to the channels and EUs through internal buses. All MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-64...
Page 719: Assignment Of Eus To Channel
1. The security engine in the MPC8313E is a single-channel implementation, but other variants of the SEC have been implemented with 1, 2, and 4 channels. Although not necessary for a single-channel SEC, dynamic assignment of EUs to the channel is maintained to improve software compatibility with other SEC-enhanced processors.
Page 720: Master Read
When the SEC performs a transaction as master, it is possible for the intended slave to terminate the transfer due to an error. SEC transaction requests are posted to the MPC8313E target queue, after which the MPC8313E takes responsibility for completing the transaction or signaling error. An error in an SEC-initiated transaction will also be reported by the SEC through the channel interrupt status register.
Page 721: Controller Registers
14-41, is used to check the assignment status of a EU to the channel. A 1-bit field indicates to the channel whether or not the EU is assigned. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-67...
Page 722: Interrupt Mask Register (Imr)
For normal operation, the IMR should be programmed as follows: Unmask the channel interrupts while masking EU interrupts. The channels will generate the appropriate interrupts to the host. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-68...
Page 723 Field — Subfield Reset 0x0000 Addr 0x 3_100C Field — MDEU — AESU — Subfield Reset 0x0000 Addr 0x 3_100C Figure 14-42. Interrupt Mask Register (IMR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-69...
Page 724: Interrupt Status Register (Isr)
(ICR). Figure 14-43 shows the bit positions of each potential interrupt source. The bit fields are described in Table 14-39. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-70 Freescale Semiconductor...
Page 725: Interrupt Clear Register (Icr)
When an ICR bit is written, it will automatically clear itself one cycle later. That is, it is not necessary to write a ‘0’ to a bit position which has been written with a ‘1’. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 726 Field — Subfield Reset 0x0000 Addr 0x 3_101C Field — MDEU — AESU — Subfield Reset 0x0000 Addr 0x 3_101C Figure 14-44. Interrupt Clear Register (ICR) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-72 Freescale Semiconductor...
Page 727: Identification Register (Id)
SEC 2.2. The value of this register is always 0x0000_0000_0002_00A0, indicating that this is the first version of SEC2.2. Field — VERSION Reset 0x0000_0000_0002_00A0 Addr 0x 3_1BF8 Figure 14-46. IP Block Revision Register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 14-73...
Page 728: Master Control Register (Mcr)
1 Global reset 14.6.5 Snooping by Caches SEC transactions can be snooped by the MPC8313E cache if defined as global. This definition is programmed in the master control register MCR[GI]. See 14.6.4.7, “Master Control Register (MCR),” more details. Note that SEC transactions are defined as global by default.
Page 729: Power Saving Mode
14.6.6 Interrupts The SEC generates a single interrupt to the MPC8313E programmable interrupt controller. The user allows interrupts from the SEC to be reported to the CPU by setting the mask bit in SIMSR_H[SEC]. The user can control which events cause an interrupt by configuring the SEC interrupt mask register (IMR).
Page 730 Security Engine (SEC) 2.2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 14-76 Freescale Semiconductor...
Page 731 NOTE The eTSECs do not support TBI, GMII, and FIFO operating modes, so all references to these interfaces and features should be ignored for this device. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-1...
Page 732 • Support for different Ethernet physical interfaces: — 10/100 Mbps IEEE 802.3 MII and RMII — 10/100 Mbps RGMII — 1000 Mbps full-duplex RGMII and RTBI MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-2 Freescale Semiconductor...
Page 733 — Programmable Ethernet preamble insertion and extraction of up to 7 bytes • MAC address recognition: — Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-3...
Page 734 If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set), the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send PAUSE frames. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-4 Freescale Semiconductor...
Page 735 Standard Ethernet interface management information base (MIBs) can be generated through the RMON MIB counters. • Internal loop back supported for all interfaces except when configured for half-duplex operation MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-5...
Page 736: External Signals Description
RTBI (RX_CLK rising)—RCG bits 3:0, input RTBI (RX_CLK falling)—RCG bits 8:5, input RMII—RXD[1:0] receive data bits, input RMII—RXD[3:2] are unused TSEC n _RX_ER MII, RMII—Receive error, input — RGMII, RTBI—Unused MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-6 Freescale Semiconductor...
Page 737 Timer current time is equal to or greater than alarm time comparator register. User reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external output pin). SD_REF_CLK, SerDes PLL reference clock (and complement) — SD_REF_CLK MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-7...
Page 738 This signal feeds back the uninverted transmit clock in MII mode, but feeds back an inverted transmit clock in RTBI or RGMII modes. This signal is driven low unless transmission is enabled. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-8 Freescale Semiconductor...
Page 739 RCG[8:5] are received on the falling edge of TSEC n _RX_CLK. In RMII mode, TSEC n _RXD[1:0] represents RXD[1:0], which is considered valid when TSEC n _RX_DV (CRS_DV) is asserted, or invalid otherwise. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-9...
Page 740 1588 timer alarm 1. Timer current time is equal to or greater than alarm time comparator register. User reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external output pin) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-10 Freescale Semiconductor...
Page 741: Top-Level Module Memory Map
Top-Level Module Memory Map Each of the eTSECs is allocated 4 Kbytes of memory-mapped space. The space for each eTSEC is divided as indicated in Table 15-3. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-11...
Page 742: Detailed Memory Map
Table 15-4. Module Memory Map eTSEC1 Name Access Reset Section/Page Offset eTSEC General Control and Status Registers 0x2_4000 TSEC_ID*—Controller ID register 0x0124_0106 15.5.3.1.1/15-22 0x2_4004 TSEC_ID2*—Controller ID register 0x0030_00F0 15.5.3.1.2/15-23 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-12 Freescale Semiconductor...
Page 743 0x2_4194 TBPTR2*—TxBD pointer for ring 2 All zeros 15.5.3.2.9/15-46 0x2_4198 Reserved — — — 0x2_419C TBPTR3*—TxBD pointer for ring 3 All zeros 15.5.3.2.9/15-46 0x2_41A0 Reserved — — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-13...
Page 744 All zeros 15.5.3.2.12/15-48 0x2_42C8 TMR_TXTS2_H* - Tx time stamp high (set 2) All zeros 15.5.3.2.12/15-48 0x2_42CC TMR_TXTS2_L* - Tx time stamp high (set 2) All zeros 15.5.3.2.12/15-48 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-14 Freescale Semiconductor...
Page 745 0x2_43B4 RBPTR6*—RxBD pointer for ring 6 All zeros 15.5.3.3.11/15-62 0x2_43B8 Reserved — — — 0x2_43BC RBPTR7*—RxBD pointer for ring 7 All zeros 15.5.3.3.11/15-62 0x2_43C0– Reserved — — — 0x2_44400 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-15...
Page 746 0x2_4528 MIIMADD—MII management address All zeros 15.5.3.5.8/15-74 0x2_452C MIIMCON—MII management control All zeros 15.5.3.5.9/15-75 0x2_4530 MIIMSTAT—MII management status All zeros 15.5.3.5.10/15-75 0x2_4534 MIIMIND—MII management indicator All zeros 15.5.3.5.11/15-76 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-16 Freescale Semiconductor...
Page 747 0x2_45B8 MAC15ADDR1*—MAC exact match address 15, part 1 All zeros 0x2_45BC MAC15ADDR2*—MAC exact match address 15, part 2 All zeros 0x2_45C0– Reserved — — — 0x2_467C MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-17...
Page 748 15.5.3.6.27/15-93 0x2_46EC TBCA—Transmit broadcast packet counter All zeros 15.5.3.6.28/15-93 0x2_46F0 TXPF—Transmit PAUSE control frame counter All zeros 15.5.3.6.29/15-94 0x2_46F4 TDFR—Transmit deferral packet counter All zeros 15.5.3.6.30/15-94 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-18 Freescale Semiconductor...
Page 749 0x2_4814 IGADDR5—Individual/group address register 5 All zeros 0x2_4818 IGADDR6—Individual/group address register 6 All zeros 0x2_481C IGADDR7—Individual/group address register 7 All zeros 0x2_4820– Reserved — — — 0x2_487C MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-19...
Page 750 0x2_4C5C RFBPTR3*—Last Free RxBD pointer for ring 3 All zeros 15.5.3.9.2/15-110 0x2_4C60 Reserved — — — 0x2_4C64 RFBPTR4*—Last Free RxBD pointer for ring 4 All zeros 15.5.3.9.2/15-110 0x2_4C68 Reserved — — — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-20 Freescale Semiconductor...
Page 751 0x2_4E7C 0x2_4E80 TMR_FIPER1* - Timer fixed period interval 0xFFFF_FFFF 15.5.3.10.13/15-121 0x2_4E84 TMR_FIPER2* - Timer fixed period interval 0xFFFF_FFFF 0x2_4E88 TMR_FIPER*3 - Timer fixed period interval 0xFFFF_FFFF MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-21...
Page 752: Memory-Mapped Register Descriptions
The controller ID register (TSEC_ID) is a read-only register. The TSEC_ID register is used to identify the eTSEC block and revision. Offset eTSEC1:0x2_4000; eTSEC2:0x2_5000 Access: Read only 15 16 23 24 TSEC_ID TSEC_REV_MJ TSEC_REV_MN Reset 0 Figure 15-2. TSEC_ID Register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-22 Freescale Semiconductor...
Page 753 30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on 50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 754: Interrupt Event Register (Ievent)
Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts because these errors are visible to network management through the MIB counters. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-24 Freescale Semiconductor...
Page 755 MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the size of its register. 0 MIB count not exceeding its register size. 1 MIB count exceeds its register size. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-25...
Page 756 0 Receive buffer descriptor not updated. 1 Receiver buffer descriptor updated. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-26 Freescale Semiconductor...
Page 757 1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set this indicates that the filer exhausted all of its table entries without a rule match. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 758: Interrupt Mask Register (Imask)
All zeros RXBEN — MAGEN MMRDEN MMWREN GRSCEN Reset All zeros RXFEN — FGPIEN FIREN FIQEN DPEEN PERREN Reset All zeros Figure 15-5. IMASK Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-28 Freescale Semiconductor...
Page 759 FIREN Filer invalid result interrupt enable FIQEN Filed frame to invalid queue interrupt enable DPEEN Data parity error interrupt enable PERREN Receive frame parse error enable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-29...
Page 760: Error Disabled Register (Edis)
LC condition occurs. 1 Do not set IEVENT[LC] nor the buffer descriptor LC field, and do not halt buffer descriptor queue if LC condition occurs. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-30 Freescale Semiconductor...
Page 761: Ethernet Control Register (Ecntrl)
Access: Mixed — Reset All zeros — GMIIM TBIM RPM RMM SGMIIM — CLRCNT AUTOZ STEN — R100M Reset All zeros Figure 15-7. ECNTRL Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-31...
Page 762 Reduced-pin mode for 10/100 interfaces. If this bit is set, an RMII pin interface is expected. RMM must be 0 if RPM = 1. This register can be pin-configured at reset to 0 or 1. 0 Non-RMII interface mode 1 RMII interface mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-32 Freescale Semiconductor...
Page 763: Pause Time Value Register (Ptv)
512 bit times. The pause time can range from 0 to 65,535 pause_quanta, or 0 to 33,553,920 bit times. See Section 15.6.2.9, “Flow Control,” for additional details. Figure 15-8 describes the definition for the PTV register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-33...
Page 764: Dma Control Register (Dmactrl)
17–23 — Reserved TDSEN Tx Data snoop enable. 0 Disables snooping of all transmit frames from memory. 1 Enables snooping of all transmit frames from memory. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-34 Freescale Semiconductor...
Page 765 RTBI) for MII management configuration. The TBI registers are accessed at the offset of TBIPA. For detailed descriptions of the TBI registers (the MII register set for the ten-bit interface) refer to Section 15.5.4, “Ten-Bit Interface (TBI).” MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-35...
Page 766: Etsec Transmit Control And Status Registers
0 IP header checksum generation is disabled even if enabled in a transmit frame control block. 1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the current transmit frame control block. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-36 Freescale Semiconductor...
Page 767 DMACTRL[GTS] or reception of a PAUSE frame. 0 No request for Tx PAUSE frame pending or transmission complete. 1 Software request for Tx PAUSE frame pending. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-37...
Page 768: Transmit Status Register (Tstat)
THLT3 THLT4 THLT5 THLT6 THLT7 — Reset All zeros TXF0 TXF1 TXF2 TXF3 TXF4 TXF5 TXF6 TXF7 — Reset All zeros Figure 15-12. TSTAT Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-38 Freescale Semiconductor...
Page 769 Repeatable error conditions which cause halt include: Bus error: • Invalid BD or data address • Uncorrectable error on BD or data read TxBD programming errors: • Ready=1 and length=0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-39...
Page 770 Repeatable error conditions which cause halt include: Bus error: • Invalid BD or data address • Uncorrectable error on BD or data read TxBD programming errors: • Ready=1 and length=0 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-40 Freescale Semiconductor...
Page 771 TXF6 Transmit frame event occurred on ring 6. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting a frame from this ring. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-41...
Page 772: Default Vlan Control Word Register (Dfvlan)
This is the default value used for the virtual-LAN identifier in VLAN-tagged frames. A value of zero is defined as the null VLAN, however field PRI may be still set independently. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-42...
Page 773: Transmit Interrupt Coalescing Register (Txic)
TxBD[I] bit set. The threshold value is represented in units of 64 clock periods as specified by the timer clock source (TXIC[ICCS[). The value of ICTT must be greater than zero to avoid unpredictable behavior. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-43...
Page 774: Transmit Queue Control Register (Tqueue)
When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register determines the weighting applied to each transmit queue for queues 0 to 3. For priority-based scheduling, MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-44...
Page 775: Txbd Ring 4–7 Weighting Register (Tr47Wt)
Queuing (MWRR).” Figure 15-17 describes the definition for the TR47WT register. Offset eTSEC1:0x2_4144; eTSEC2:0x2_5144 Access: Read/Write 15 16 23 24 Reset All zeros Figure 15-17. TR47WT Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-45...
Page 776: Transmit Data Buffer Pointer High Register (Tbdbph)
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-46...
Page 777: Transmit Descriptor Base Address Registers (Tbase0–Tbase)
BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit function on the associated ring. 29–31 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-47...
Page 778: Transmit Time Stamp Identification Register (Tmr_Txts1–2_Id)
TMR_TXTSn_H/L register. Table 15-27. TMR_TXTS n _H/L Register Field Descriptions Bits Name Description 0–63 TXTS_H/L Time stamp field of the transmitted PTP packet’s start of frame detection. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-48 Freescale Semiconductor...
Page 779: Etsec Receive Control And Status Registers
For FIFO packet interface connections, the RFC signal is asserted. 0 Disabled. This is the default 1 Enabled, calculate the free BDs in each active ring and assert link layer flow control if required. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-49...
Page 780 DA are accepted and the M (MISS) bit is set in the receive BD. PROM Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-50 Freescale Semiconductor...
Page 781: Receive Status Register (Rstat)
A write with a value of 1 re-enables the queue for receiving. 0 This queue is enabled for reception. (That is, it is not halted) 1 All controller receive activity to this queue is halted. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-51...
Page 782 RXF4 Receive frame event occurred on ring 4. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a frame to this ring. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-52 Freescale Semiconductor...
Page 783 RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 784: Receive Queue Control Register (Rqueue)
ARB property. Through RBIFX a custom ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-54...
Page 785 B2OFFSET Offset relative to the header defined by B2CTL that locates byte 2 of property ARB. An effective offset of zero points to the first byte of the specified header. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 786: Receive Queue Filer Table Address Register (Rqfar)
Section 15.6.4.2, “Receive Queue Filer.” The word accessed through RQFCR is defined by the current value of RQFAR. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-56 Freescale Semiconductor...
Page 787 1 Match property[PID] against RQPROP. If matched, enter cluster. Otherwise, skip all rules up to and including the next rule while CLE = 1 and AND = 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 788: Receive Queue Filer Table Property Register (Rqfpr)
Figure 15-30. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition Offset eTSEC1:0x2_433C; eTSEC2:0x2_533C Access: Read/Write — Reset All zeros — Reset All zeros Figure 15-31. Receive Queue Filer Table Property ID1 Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-58 Freescale Semiconductor...
Page 789 DAH Destination MAC address, most significant 24 bits. Defaults to 0x000000. 0100 0–7 — Reserved, should be written with zero. 8–31 Destination MAC address, least significant 24 bits. Defaults to 0x000000. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-59...
Page 790 Reserved, should be written with zero. 29–31 VLAN user priority (as per IEEE Std 802.1p). This value defaults to 000 (best effort priority) if no VLAN tag was found. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-60 Freescale Semiconductor...
Page 791: Maximum Receive Buffer Length Register (Mrblr)
MRBLR. Offset eTSEC1:0x2_4340; eTSEC2:0x2_5340 Access: Read/Write 15 16 25 26 — MRBL — Reset All zeros Figure 15-32. MRBLR Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-61...
Page 792: Receive Data Buffer Pointer High Register (Rbdbph)
Rx buffer is in use (after a GRACEFUL STOP RECEIVE command is issued and the frame completes its reception) in order to change the next RxBD eTSEC receives. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-62...
Page 793: Receive Descriptor Base Address Registers (Rbase0–Rbase)
Receive time stamp register (RXTS_H/L). This register holds the value present in TMR_CNT_H/L when the eTSEC detects a new incoming Ethernet frame. This register is only updated when the precision time MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 794: Mac Functionality
CRS, and following a carrier event, times the IPG using the non-back-to-back IPG configuration values that include support for the optional MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-64...
Page 795: Handling Packet Collisions
(THDF) is set (TCTRL[THDF]). If the medium is idle, the eTSEC raises carrier by transmitting preamble. Other stations on the half-duplex network then defer to the carrier. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 796: Controlling Phy Links
While enabled, the length of MII management frames are reduced from 64 clocks to 32 clocks. This effectively doubles the efficiency of the interface. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-66 Freescale Semiconductor...
Page 797: Mac Registers
Reserved Loop Back Loop back. This bit is cleared by default. 0 Normal operation. 1 Loop back the MAC transmit outputs to the MAC receive inputs. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-67...
Page 798: Mac Configuration 2 Register (Maccfg)
Length Full — PreAmRxEN PreAmTxEN MPEN PAD/CRC CRC EN Length Mode Frame check Duplex Reset 0 1 1 1 0 0 Figure 15-38. MACCFG2 Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-68 Freescale Semiconductor...
Page 799 0 No length field checking is performed. 1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length. Transmitted frames are not checked. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-69...
Page 800: Inter-Packet Gap/Inter-Frame Gap Register (Ipgifg)
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which follows the two-thirds/one-third guideline. — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-70 Freescale Semiconductor...
Page 801: Half-Duplex Register (Hafdup)
Back pressure no backoff. This bit is cleared by default. BackOff 0 The Tx MAC follows the binary exponential back off rule. 1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-71...
Page 802: Maximum Frame Length Register (Maxfrm)
PHYs be accessed and configured. Note: when an eTSEC is configured to use RTBI, configuration of the RTBI (described in Section 15.5.4, “Ten-Bit Interface (TBI)”) is done through the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-72 Freescale Semiconductor...
Page 803: Mii Management Command Register (Miimcom)
The MIIMCOM register is written by the user. Figure 15-43 describes the definition for MIIMCOM. Offset eTSEC1:0x2_4524 Access: Read/Write — Scan Cycle Read Cycle Reset All zeros Figure 15-43. MIIMCOM Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-73...
Page 804: Mii Management Address Register (Miimadd)
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be accessed. Its default value is 0x00. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-74 Freescale Semiconductor...
Page 805: Mii Management Control Register (Miimcon)
0–15 — Reserved 16–31 PHY Status Following an MII Mgmt read cycle, the 16-bit data can be read from this location. Its default value is 0x0000. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-75...
Page 806: Mii Management Indicator Register (Miimind)
Figure 15-48. Interface Status Register Definition Table 15-52 describes the fields of the FSTAT register. Table 15-52. IFSTAT Field Descriptions Bits Name Description 0–21 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-76 Freescale Semiconductor...
Page 807: Mac Station Address Part 1 Register (Macstnaddr)
Station Address, 3rd Octet This field holds the third octet of the station address. The third – octet (station address bits 16 23) defaults to a value of 0x0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-77...
Page 808: Mac Station Address Part 2 Register (Macstnaddr)
Exact Match Address, Exact Match Address, 6th Octet 5th Octet 4th Octet 3rd Octet Reset All zeros Figure 15-51. MAC Exact Match Address n Part 1 Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-78 Freescale Semiconductor...
Page 809: Mac Exact Match Address 1–15 Part 2 Registers
RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3, RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 810: Transmit And Receive 64-Byte Frame Counter (Tr)
TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and received which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-80...
Page 811: Transmit And Receive 65- To 127-Byte Frame Counter (Tr)
10–31 TR255 Transmit and receive 128- to 255-byte frame counter—Increments for each good or bad frame transmitted and received which is 128–255 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 812: Transmit And Receive 256- To 511-Byte Frame Counter (Tr)
TR1K Increments for each good or bad frame transmitted and received which is 512–1023 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-82 Freescale Semiconductor...
Page 813: Transmit And Receive 1024- To 1518-Byte Frame Counter (Trmax)
TRMGV Increments for each good or bad frame transmitted and received which is 1519–1522 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-83...
Page 814: Receive Byte Counter (Rbyt)
RFCS register. Offset eTSEC1:0x2_46A4; eTSEC2:0x2_56A4 Access: Read/Write 15 16 — RFCS Reset All zeros Figure 15-62. Receive FCS Error Counter Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-84 Freescale Semiconductor...
Page 815: Receive Multicast Packet Counter (Rmca)
Receive broadcast packet counter. Increments for each broadcast frame with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN), excluding multicast frames. Does not include range/length errors. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 816: Receive Control Frame Packet Counter (Rxcf)
Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is received with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-86...
Page 817: Receive Unknown Opcode Packet Counter (Rxuo)
Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or 1522 (VLAN) which contains an invalid FCS and is not an integral number of bytes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 818: Receive Frame Length Error Counter (Rflr)
0–15 — Reserved 16–31 RCDE Receive code error counter. Increments each time a valid carrier is present and at least one invalid data symbol is detected. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-88 Freescale Semiconductor...
Page 819: Receive Carrier Sense Error Counter (Rcse)
Receive undersize packet counter. Increments each time a frame is received which is less than 64 bytes in length and contains a valid FCS and were otherwise well formed. This count does not include range length errors. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-89...
Page 820: Receive Oversize Packet Counter (Rovr)
Receive fragments counter. Increments for each frame received which is less than 64 bytes in length and contains an invalid FCS. This includes integral and non-integral lengths. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-90 Freescale Semiconductor...
Page 821: Receive Jabber Counter (Rjbr)
Reserved 16–31 RDRP Receive dropped packets counter. Increments for frames received which are streamed to system but are later dropped due to lack of system resources. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-91...
Page 822: Transmit Byte Counter (Tbyt)
10–31 TPKT Transmit packet counter. Increments for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-92...
Page 823: Transmit Multicast Packet Counter (Tmca)
Transmit broadcast packet counter. Increments for each broadcast frame transmitted (excluding multicast frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 824: Transmit Pause Control Frame Counter (Txpf)
TDFR Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission attempt. This count does not include frames involved in collisions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-94 Freescale Semiconductor...
Page 825: Transmit Excessive Deferral Packet Counter (Tedf)
Table 15-88. TSCL Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TSCL Transmit single collision packet counter. Increments for each frame transmitted which experienced exactly one collision during transmission. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-95...
Page 826: Transmit Multiple Collision Packet Counter (Tmcl)
Transmit late collision packet counter. Increments for each frame transmitted which experienced a late collision during a transmission attempt. Late collisions are defined using the collision window field of the half-duplex [26:31] register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-96 Freescale Semiconductor...
Page 827: Transmit Excessive Collision Packet Counter (Txcl)
DO and RD circuits (That is, transmitting and receiving at the same time). Note: This count does not include collisions that result in an excessive collision condition. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-97...
Page 828: Transmit Drop Frame Counter (Tdrp)
Table 15-94. TJBR Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TJBR Transmit jabber frame counter. Increments for each oversized transmitted frame with an incorrect FCS value. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-98 Freescale Semiconductor...
Page 829: Transmit Fcs Error Counter (Tfcs)
Reserved 20–31 TXCF Transmit control frame counter. Increments for every control frame with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-99...
Page 830: Transmit Oversize Frame Counter (Tovr)
Table 15-98. TUND Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TUND Transmit undersize frame counter. Increments for every frame less then 64 bytes, with a correct FCS value. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-100 Freescale Semiconductor...
Page 831: Transmit Fragment Counter (Tfrg)
Carry register 1 TR64 counter carry bit C1127 Carry register 1 TR127 counter carry bit C1255 Carry register 1 TR255 counter carry bit C1511 Carry register 1 TR511 counter carry bit MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-101...
Page 832 Carry register 1 ROVR counter carry bit C1RFR Carry register 1 RFRG counter carry bit C1RJB Carry register 1 RJBR counter carry bit C1RDR Carry register 1 RDRP counter carry bit MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-102 Freescale Semiconductor...
Page 833: Carry Register 2 (Car)
Carry register 2 TSCL counter carry bit C2TMA Carry register 2 TMCL counter carry bit C2TLC Carry register 2 TLCL counter carry bit C2TXC Carry register 2 TXCL counter carry bit MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-103...
Page 834: Carry Mask Register 1 (Cam)
Mask register 1 RPKT counter carry bit mask M1RFC Mask register 1 RFCS counter carry bit mask M1RMC Mask register 1 RMCA counter carry bit mask MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-104 Freescale Semiconductor...
Page 835: Carry Mask Register 2 (Cam)
Table 15-103. CAM2 Field Descriptions Bits Name Description 0–11 — Reserved M2TJB Mask register 2 TJBR counter carry bit mask M2TFC Mask register 2 TFCS counter carry bit mask MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-105...
Page 836: Receive Filer Rejected Packet Counter (Rrej)
REJ flag or due to filing to a RxBD ring that was not enabled (see IEVENT[FIQ] error). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-106...
Page 837: Hash Function Registers
The GADDRn registers are written by the user. Together these registers represent, depending on RCTRL[GHTX], either the 256 entries of the group address hash table, or the last 256 entries of the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 838: Dma Attribute Registers
Figure 15-103 describes the definition for the ATTR register. Offset eTSEC1:0x2_4BF8; eTSEC2:0x2_5BF8; Access: Read/Write — RDSEN RBDSEN — Reset All zeros Figure 15-103. ATTR Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-108 Freescale Semiconductor...
Page 839: Lossless Flow Control Configuration Registers
Figure 15-104 describes the definition for the RQPRMn register. Offset eTSEC1:0x2_4C00+4× n ; eTSEC2:0x2_5C00+4× n Access: Read/Write FBTHR Reset All zeros Figure 15-104. RQPRM Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-109...
Page 840: Ieee 1588-Compatible Timestamping Registers
Ethernet controller memory space (See Section 15.5.3.2.11, “Transmit Time Stamp Identification Register (TMR_TXTS1–2_ID),” and Section 15.5.3.2.12, “Transmit Time Stamp Register (TMR_TXTS1–2_H/L)”) in conjunction with the following common registers, which are MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-110 Freescale Semiconductor...
Page 841 1 Fiper1 pulse is looped back into Trigger1 input. PP2L Fiper2 pulse loopback mode enabled. 0 Trigger2 input is based upon normal external trigger input. 1 Fiper2 pulse is looped back into Trigger2 input. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-111...
Page 842 Bypass drift compensated clock 0 64-bit clock counter is incremented on the accumulator overflow 1 64-bit clock counter is directly driven from the external oscillator ignoring accumulator overflow MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-112 Freescale Semiconductor...
Page 843: Timer Event Register (Tmr_Tevent)
Table 15-111. TMR_TEVENT Register Field Descriptions Bits Name Description 0–6 — Reserved ETS2 External trigger 2 timestamp sampled 0 external trigger timestamp not sampled 1 external trigger timestamp sampled MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-113...
Page 844: Timer Event Mask Register (Tmr_Temask)
TMR_TEMASK register. Offset eTSEC1:0x2_4E08 Access: Read/Write — ETS2EN ETS1EN — ALM2EN ALM1EN Reset All zeros — PP1EN PP2EN — Reset All zeros Figure 15-108. TMR_TEMASK Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-114 Freescale Semiconductor...
Page 845: Timer Ptp Packet Event Register (Tmr_Pevent)
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register. 0 PTP packet not transmitted 1 PTP packet has been transmitted MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-115...
Page 846: Timer Event Mask Register (Tmr_Pemask)
ID which the incoming packet will be sent to is captured in this register. This register update is synchronized with the RXF interrupt of the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-116...
Page 847: Timer Counter Register (Tmr_Cnt_H/L)
TMR_CNT_H/L register. Offset eTSEC1:0x2_4E18 (H); 0x2_4E1C (L) Access: Read/Write 31 32 TMR_CNT_H TMR_CNT_L Reset All zeros Figure 15-111. TMR_CNT_H Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-117...
Page 848: Timer Drift Compensation Addend Register (Tmr_Add)
Timer drift compensation addend register value. It is programmed with a value of 2^32/FreqDivRatio. For example, TimerOsc = 50 MHz NominalFreq = 40 MHz FreqDivRatio = 1.25 ADDEND = ceil(2^32/1.25) = 0xCCCC_CCCD MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-118 Freescale Semiconductor...
Page 849: Timer Accumulator Register (Tmr_Acc)
The timer offset register is used to provide current time by adding its value to the clock counter. Figure 15-115 describes the definition of the TMROFF_H/L register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-119...
Page 850: Alarm Time Comparator Register (Tmr_Alarm1–2_H/L)
In FS mode the alarm trigger is used as an indication to the fiper start down counting. Only alarm 1 supports this mode. In FS mode, alarm polarity bit should be configured to 0 (rising edge). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-120...
Page 851 The three registers in eTSEC1 are shared for all eTSECs. Figure 15-117 describes the definition for the TMR_FIPER register. Offset eTSEC1:0x2_4E80+4* n Access: Read/Write FIPER Reset 1 Figure 15-117. TMR_FIPER n Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-121...
Page 852: External Trigger Stamp Register (Tmr_Etts1–2_H/L)
8B10B encoding module. After the last byte of the FCS field is signaled through the GMII, the MAC de-asserts TX_EN. The eTSEC then outputs an End_of_Packet symbol. Then, depending on the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-122...
Page 853: B10B Encoding
Auto-Negotiation re-starts. After Auto-Negotiation is completed the TBI MII Status Register SR[AN done] in set. In this mode, packets may be received from the link partner. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-123...
Page 854: Tbi Mii Set Register Descriptions
16 bits 15.5.4.3.10/15-134 R = Read-only, WO = Write Only, R/W = Read and Write, LH = Latches High, LL = Latches Low, SC = Self-clearing, MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-124 Freescale Semiconductor...
Page 855: Control Register (Cr)
Its default is bit[2] = ‘0’; bit[9] = ’1’. Maximum Operating Speed Bit 2 Bit 9 Reserved Reserved 1000 Mbps Reserved 10–15 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-125...
Page 856: Status Register (Sr)
Extended capability. This bit indicates that the PHY contains the extended set of registers (those beyond Ability control and status). Returns 1 on read. This bit is read-only. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-126 Freescale Semiconductor...
Page 857: An Advertisement Register (Ana)
For priority resolution information consult Table 15-129. PAUSE bit[8] ASM_DIR bit[7] Capability No PAUSE Asymmetric PAUSE toward link partner Symmetric PAUSE Both symmetric PAUSE and Asymmetric PAUSE toward local device MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-127...
Page 858 Disable PAUSE receive Disable PAUSE transmit Enable PAUSE transmit Enable PAUSE receive Disable PAUSE receive Enable PAUSE transmit Enable PAUSE transmit Enable PAUSE receive Enable PAUSE receive MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-128 Freescale Semiconductor...
Page 859: An Link Partner Base Page Ability Register (Anlpbpa)
Asymmetric PAUSE toward local device Half Half-duplex capability. This bit is read-only. Duplex 0 Link partner is not capable of half-duplex mode. 1 Link partner is capable of half-duplex mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-129...
Page 860: An Expansion Register (Anex)
ANNPT register. Offset 0x07 Access: Mixed R Next Toggle — Ack2 Message/Un-formatted Code Field Page Page Reset All zeros Figure 15-124. AN Next Page Transmit Register Definition MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-130 Freescale Semiconductor...
Page 861: An Link Partner Ability Next Page Register (Anlpanp)
Next page. The link partner sets and clears this bit. 0 Last page from link partner 1 Additional next pages to follow — Reserved. (Ignore on read) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-131...
Page 862: Extended Status Register (Exst)
1000T half-duplex capability. Returns 0 on read. This bit is read-only. 0 PHY cannot operation in 1000BASE-T half-duplex mode. 1 PHY can operate in 1000BASE-T half-duplex mode. 4–15 — Reserved MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-132 Freescale Semiconductor...
Page 863: Jitter Diagnostics Register (Jd)
Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired Pattern custom pattern which is continuously transmitted. Its default is 0x000. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-133...
Page 864: Tbi Control Register (Tbicon)
(parallel) mode, must be provided via the TBI receive clock 0 (TSEC n _RX_CLK) external signal. If operating in SGMII mode, this clock is provided on-chip by the SerDes block. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-134 Freescale Semiconductor...
Page 865: Connecting To Physical Interfaces On Ethernet
0 is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that are not used must be pulled low on the board. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 866: Media-Independent Interface (Mii)
PHY. The RMII is implemented as defined by the RMII Specification of the RMII Consortium, as of March 20, 1998. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-136 Freescale Semiconductor...
Page 867: Reduced Gigabit Media-Independent Interface (Rgmii)
Ethernet controllers’ module connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a 9/22/00. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-137...
Page 868: Reduced Ten-Bit Interface (Rtbi)
RTBI including the signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC immediately begins auto-negotiation with the SerDes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-138 Freescale Semiconductor...
Page 869 SGMII including the signals required to establish eTSEC module connection with a PHY. Note that in SGMII the eTSEC utilizes the on-chip TBI PHY in addition to the SerDes interface. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-139...
Page 870 The management signals (MDC and MDIO) may be common to all of the Ethernet controllers’ connections in the system, assuming that each PHY has a different management address. Figure 15-133. eTSEC-SGMII Connection MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-140 Freescale Semiconductor...
Page 871: Ethernet Physical Interfaces Signal Summary
No. of Signals No. of Signals No. of (TSEC n _) Signals (TSEC n _) Signals (TSEC n _) Signals GTX_CLK GTX_CLK GTX_CLK TX_CLK TxD[0] TxD[0 TCG[0]/TCG[5] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-141...
Page 872 Signals SD n _RX[ n ] SGMII receive data (differential) SD n _TX[ n ] SGMII transmit data (differential) SD n _REF_CLK Reference clock (differential) — MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-142 Freescale Semiconductor...
Page 873: Gigabit Ethernet Controller Channel Operation
1. Set and clear MACCFG1 [Soft_Reset] 2. Initialize MACCFG2 3. Initialize MAC station address 4. Set up the PHY using the MII Mgmt Interface 5. Configure the GMII MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-143...
Page 874: Soft Reset And Reconfiguring Procedure
3. Set SOFT_RESET bit in MACCFG1 register (Note that SOFT_RESET must remain set for at least 3 TX clocks before proceeding.) 4. Clear SOFT_RESET bit in MACCFG1 register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-144 Freescale Semiconductor...
Page 875: Gigabit Ethernet Frame Transmission
Data stored in the Tx FIFO is re-transmitted in case of a collision. This avoids unnecessary memory traffic. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 876: Gigabit Ethernet Frame Reception
After a hardware reset, the software driver clears the RSTAT register and sets MACCFG1[RX_EN]. The Ethernet receiver is enabled and immediately starts processing receive frames. The MAC checks for when MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-146...
Page 877 (preamble sequence and start of frame delimiter), it resumes receiving, and the first valid frame received is placed in the next available RxBD. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-147...
Page 878: Ethernet Preamble Customization
PreOct4 Octet #4 of custom transmit preamble. This is the fifth octet of preamble sent. 8–15 PreOct5 Octet #5 of custom transmit preamble. This is the sixth octet of preamble sent. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-148 Freescale Semiconductor...
Page 879: User-Visible Preamble Reception
The RMON MIB group 1, RMON MIB group 2, RMON MIB group 3, RMON MIB group 9, RMON MIB2, and the IEEE 802.3 Ethernet MIB are supported. For RMON statistics and their corresponding counters, see the memory map. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-149...
Page 880: Frame Recognition
Enhanced Three-Speed Ethernet Controllers 15.6.2.7 Frame Recognition The Ethernet controller performs frame recognition using destination address (DA) recognition. A frame can be rejected or accepted based on the outcome. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-150 Freescale Semiconductor...
Page 881: Destination Address Recognition And Frame Filtering
In promiscuous mode, the eTSEC accepts all received frames regardless of DA. Note, however, that Ethernet frame filtering simply restricts the traffic seen by the receive queue filer. Therefore even in MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 882: Hash Table Algorithm
{IGADDR, GADDR} set, while bits H[4:0] select a bit within the 32-bit register. For example, if H[8:5] = 7, IGADDR7 is selected, whereas H[8:5] = 9 selects GADDR1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-152...
Page 883 512-bin hash table increases, the vast majority of the hash table bits are set, preventing only a small fraction of frames from reaching memory. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 884: Magic Packet Mode
Start frame delimiter Destination address 01-80-C2-00-00-01 Multicast address reserved for use in MAC frames (or MAC station address) Source address — Length/type 88-08 Control frame type MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-154 Freescale Semiconductor...
Page 885: Interrupt Handling
Because the eTSEC pre-fetches BDs, the BD table must be big enough so that there is always another empty BD to pre-fetch, otherwise a BSY error occurs. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 886: Interrupt Coalescing
To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may enable and configure interrupt coalescing to deliberately group frame interrupts, reducing the total number of MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-156...
Page 887: Interrupt Coalescing By Timer Threshold
25.2 ms The transmit timer threshold counter is reset to the value in TXIC[ICTT] and begins counting down on transmission of the frame following an interrupt. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-157...
Page 888: Inter-Frame Gap Time
In the latter case, the relevant transmit queue is halted. In all cases, the eTSEC closes the buffer, sets TxBD[UN], IEVENT[XFUN], and IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-158 Freescale Semiconductor...
Page 889 Software must confirm the parser and filer results by checking the type/length field after the packet has been written to memory to see if it falls in this range. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 890: Tcp/Ip Off-Load
The eTSEC does not checksum transmitted packets with IPv6 routing headers or calculate TCP/UDP checksums from IP fragments. If a transmitted TCP segment requires checksum generation but MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-160...
Page 891: Frame Control Blocks
Only one FCB is inserted per frame, in the buffer pointed to by the RxBD with bit F set. TOE acceleration for receive is enabled for all frames in this case. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 892: Transmit Path Off-Load And Tx Ptp Packet Parsing
UDP protocol at layer 4. 0 Layer 4 protocol is either TCP (if TUP = 1) or undefined. 1 Layer 4 protocol is UDP if TUP = 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-162 Freescale Semiconductor...
Page 893: Receive Path Off-Load
Offset + 0 TUP CIP CTU EIP — PERR — GPFP Offset + 2 Offset + 4 Offset + 6 VLCTL Figure 15-140. Receive Frame Control Block MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-163...
Page 894 10 Inconsistent or unsupported L3 header sequence 11 Reserved — Reserved GPFP General-purpose filer event packet. This packet was filed based on matching a GPI rule sequence. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-164 Freescale Semiconductor...
Page 895: Quality Of Service (Qos) Provision
Extraction of 2-byte VLAN control field • Walk through MPLS stack and find layer 3 protocol • Walk through VLAN stack and find layer 3 protocol MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-165...
Page 896 L3(IPv4/6) and L4(TCP/UDP) parsers are as follows: • IP recognition (v4/v6, ARP, encapsulated protocol) • IP header checksum verification • IPv4/6 over IPv4/6 (tunneling)—parse headers and find layer 4 protocol MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-166 Freescale Semiconductor...
Page 897: Receive Queue Filer
RQCTRL field. The eTSEC memory map provides access to these fields by way of an address register (RQFAR) and two porthole registers (RQFCR and RQFPR). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 898: Filing Rules
The REJ field in RQCTRL controls whether the frame is to be rejected (REJ = 1) or filed (REJ = 0) upon a filing rule match. Rejected frames occupy Rx FIFO space, but do not consume memory bus cycles. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-168 Freescale Semiconductor...
Page 899: Comparing Properties With Bit Masks
(CMP = 01) or fails (CMP = 11). In this entry, RQPROP is then considered to be the assigned bit vector. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 900: Special-Case Rules
If the timer is enabled (TMR_CTRL[TE] = 1), then the interrupt dedicated for timer events (in addition to the usual receive, transmit and error interrupts) will be asserted. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-170...
Page 901: Setting Up The Receive Queue Filer Table
0x0000_0004 File priority 4 to ring 3 0x0000_0C09 000_100 1001 0x0000_0003 File priority 3 to ring 4 0x0000_1009 000_101 1001 0x0000_0002 File priority 2 to ring 5 0x0000_1409 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-171...
Page 902: Filer Example—Ip Diff-Serv Code Points Filing
20 and port number < 22. Entries 4 and 5 are initially set up to always fail (zero port number), and thus comprise empty entries that can be used at a later time. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-172...
Page 903 0x0001_0000 Check to see if ARP request flag is set by doing a =1 comparison. Enter the “ARP Request Cluster” if true. 000_000 0000 0xFFFF_FFFF ARP Cluster: Set Mask to unmask everything (Reset mask to all F’s) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-173...
Page 904 0100 0x00YY_YYYY Compare lower L2 DA bits to YY_YYYY. 000_001 1110 0x0000_ZZZZ If all of the previously consecutive ANDed conditions pass, SNMP broadcast Query has matched. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-174 Freescale Semiconductor...
Page 905: Transmission Scheduling
TxBD ring 1, and frames in TxBD ring 1 have higher priority than frames in TxBD ring 2, and so on. The scheduling decision is then achieved as follows: loop # start or S/W clear of TSATn MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-175...
Page 906: Modified Weighted Round-Robin Queuing (Mwrr)
(K = 1 to 7) = (available bandwidth) * WTk/(sum(WTi) + 6WT0) rate of queue(0) = (available bandwidth) * 7 * WT0/(sum(WTi) + 6WT0) where i = 0 to 7 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-176 Freescale Semiconductor...
Page 907: Lossless Flow Control
It is recommended that a threshold of at least fourBDs is the practical minimum for gigabit Ethernet links. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 908 Once the eTSEC determines that this threshold has been reached, back pressure is applied accordingly. The type of back pressure that is applied varies according to the physical interface that is used. • Half duplex Ethernet: No support in this mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-178 Freescale Semiconductor...
Page 909: Software Use Of Hardware-Initiated Back Pressure
The precision of this clock is dictated by the application, but generally needs to be of the order of <1uSec for high-speed machinery (for example, printing presses). MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-179...
Page 910 Supports all Ethernet modes supported by the eTSEC, including full- and half-duplex modes • Supports both master and slave modes • Supports timestamp of nano-second resolution MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-180 Freescale Semiconductor...
Page 911: Timer Logic Overview
[1588]. For transmission, the eTSEC sample point precedes the sample point specified in [1588] by at least 4-bit times (MII) or 8-bit times (GMII). For a particular mode, the eTSEC MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 912: Ptp Packet Parsing
34-35 header ID=1011] DPT-RQPFR[P EventPort Destination port number 36-37 header ID=1011] GeneralPort Sync RBIFX- choose Delay_req Control UDP data an arbitrary Follow_up extraction byte Delay_resp Management MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-182 Freescale Semiconductor...
Page 913: General Purpose Filer Rule
TXP1, and TXP2. Table 15-160. Time-Stamp Insertion Programming Requirements Requirement Behavior if requirement is not met TMR_CTRL[RTPE]=1 If TMR_CTRL[RTPE]=0, then no time-stamp is written to a TxPAL. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-183...
Page 914 Data Buffer Length=8 Data Buffer Pointer TxPAL Data Buffer Length=M TxPAL Data Buffer Pointer TxPAL Unknown Unknown FRAME 8 Bytes Figure 15-145. Buffer Format for Transmit Time-Stamp Insertion MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-184 Freescale Semiconductor...
Page 915 UDP protocol at layer 4. 0 Layer 4 protocol is either TCP (if TUP = 1) or undefined. 1 Layer 4 protocol is UDP if TUP = 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-185...
Page 916: Buffer Descriptors
Ethernet frame. Within each data BD there is a status field, a data length field, and a data pointer. The BD completely describes an MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-186...
Page 917 (RBASE n ) RxBD Status & Control Table for Ring n Data Length Buffer Pointer Rx Buffer Figure 15-147. Example of eTSEC Memory Structure for BDs MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-187...
Page 918: Transmit Data Buffer Descriptors (Txbd)
Offset + 0 PAD/CRC PRE/DEF HFE/LC CF/RL TOE/UN Offset + 2 DATA LENGTH Offset + 4 TX DATA BUFFER POINTER Offset + 6 Figure 15-149. Transmit Buffer Descriptor MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-188 Freescale Semiconductor...
Page 919 Last in frame. Written by user. 0 The buffer is not the last in the transmit frame. 1 The buffer is the last in the transmit frame. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-189...
Page 920 One or more attempts where needed to send the transmit frame. If this field is 15, then 15 or more retries were needed. The Ethernet controller updates RC after sending the buffer. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-190...
Page 921: Receive Buffer Descriptors (Rxbd)
Figure 15-151. Receive Buffer Descriptor The RxBD definition is interpreted by eTSEC hardware as if RxBDs mapped to C data structures in the manner illustrated by Figure 15-152. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-191...
Page 922 M-bit to quickly determine whether the frame was destined to this station. 0 The frame was received because of an address recognition hit. 1 The frame was received because of promiscuous mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-192 Freescale Semiconductor...
Page 923: Interface Mode Configuration
Initialization/Application Information 15.7.1 Interface Mode Configuration This section describes how to configure the eTSEC in different supported interface modes. These include the following: • • RMII MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-193...
Page 924: Mii Interface Mode
TxD[0] TxD[0] TxD[1] TxD[1] TxD[2] TxD[2] TxD[3] TxD[3] TX_EN TX_EN TX_ER TX_ER RX_CLK RX_CLK RxD[0] RxD[0] RxD[1] RxD[1] RxD[2] RxD[2] RxD[3] RxD[3] RX_DV RX_DV RX_ER RX_ER MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-194 Freescale Semiconductor...
Page 925 MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100] Perform an MII Mgmt write cycle to the external PHY Writing to MII Mgmt Control with 16-bit data intended for the external PHY register, MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-195...
Page 926 Check auto-negotiation attributes in the PHY as necessary. Clear IEVENT register, IEVENT[0000_0000_0000_0000_0000_0000_0000_0000] Initialize IMASK (Optional) IMASK[0000_0000_0000_0000_0000_0000_0000_0000] Initialize MACnADDR1/2 (Optional) MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000] Initialize GADDR n (Optional) GADDR n [0000_0000_0000_0000_0000_0000_0000_0000] Initialize RCTRL (Optional) RCTRL[0000_0000_0000_0000_0000_0000_0000_0000] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-196 Freescale Semiconductor...
Page 927: Rgmii Interface Mode
TxD[3] TxD[3]/TxD[7] TX_EN TX_CTL (TX_EN/TX_ERR) TX_ER leave unconnected RX_CLK RX_CLK RxD[0] RxD[0]/RxD[4] RxD[1] RxD[1]/RxD[5] RxD[2] RxD[2]/RxD[6] RxD[3] RxD[3]/RxD[7] RX_DV RX_CTL (RX_DV/RX_ERR) RX_ER not used not used MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-197...
Page 928 Setup the MII Mgmt clock speed, MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101] Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not less than 2.5 MHz. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-198 Freescale Semiconductor...
Page 929 When MIIMIND[BUSY]=0, read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d) MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-199...
Page 930 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-200 Freescale Semiconductor...
Page 931: Rmii Interface Mode
Table 15-171. Shared RMII Signals No. of No. of eTSEC Signals RMII Signals Function Signals Signals MDIO MDIO Management interface I/O Management interface clock TX_CLK REF_CLK Reference clock MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-201...
Page 932 Check to see if MII Mgmt write is complete. Read MII Mgmt Indicator register and check for Busy = 0, MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000] This indicates that the write cycle was completed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-202 Freescale Semiconductor...
Page 933 Setting up the MII Mgmt for a read cycle to PHY’s MII Mgmt register (write the PHY’s address and Register address), MIIMADD[0000_0000_0000_0000_0000_0010_0000_0010] the PHY Status control register is at address 0x2 and lets say the PHY Address is 0x2 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-203...
Page 934 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-204 Freescale Semiconductor...
Page 935: Rtbi Interface Mode
MDIO MDIO Management interface I/O Management interface clock ECGTX_CLK125 GTX_CLK125 Reference clock Table 15-175 describes the register initializations required to configure the eTSEC in RTBI mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-205...
Page 936 Check to see if MII Mgmt write is complete. Read MII Mgmt Indicator register and check for Busy = 0, MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000] This indicates that the write cycle was completed. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-206 Freescale Semiconductor...
Page 937 MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00x_x110_0000] Clear IEVENT register, IEVENT[0000_0000_0000_0000_0000_0000_0000_0000] Initialize IMASK (Optional) IMASK[0000_0000_0000_0000_0000_0000_0000_0000] Initialize MACnADDR1/2 (Optional) MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000] Initialize GADDR n (Optional) GADDR n [0000_0000_0000_0000_0000_0000_0000_0000] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-207...
Page 938: Sgmii Interface Support
MAC if the desired link speed is not 1 Gbps. Software can perform MII management cycles to determine the external PHY link speed and program ECNTRL and MACCFG2 accordingly. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-208 Freescale Semiconductor...
Page 939 Writing to MII Mgmt Control with 16-bit data intended for TBICON register, MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000] This sets TBI in single clock mode and MII Mode off to enable communication with SerDes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-209...
Page 940 When MIIMIND[BUSY] = 0, read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d) MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-210 Freescale Semiconductor...
Page 941 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 15-211...
Page 942 Enhanced Three-Speed Ethernet Controllers MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 15-212 Freescale Semiconductor...
Page 943 The device implements a dual-role (DR) USB module. This module may be connected to an external port. Collectively the module and external port are called the USB interface. The USB interface is shown in Figure 16-1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-1...
Page 944 — Supports enhanced host controller interface (EHCI) • Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low speed is only supported in host mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-2 Freescale Semiconductor...
Page 945: Utmi Interface
An external precision resistor of 10KΩ ± 1% is connected between this pin and ground. USB_TPA I/O This is a test pin. It should be left unconnected. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-3...
Page 946: Ulpi Interface
PHY PLL is not stable. State Asserted—PHY has data to transfer to the link. Meaning Negated—PHY has no data to transfer. Timing Synchronous to PHY_CLK. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-4 Freescale Semiconductor...
Page 947: Phy Clocks
The USBDR_CLK input provides the clocking signal for the ULPI PHY interface. The clock is 60 MHz. Detailed clock specifications are given in the appropriate hardware specifications document. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 948 0x1AC ENDPTSETUPSTAT—Endpoint setup status 0x0000_0000 16.3.2.17/16-35 0x1B0 ENDPOINTPRIME—Endpoint initialization 0x0000_0000 16.3.2.18/16-36 0x1B4 ENDPTFLUSH—Endpoint de-initialize 0x0000_0000 16.3.2.19/16-36 0x1B8 ENDPTSTATUS—Endpoint status 0x0000_0000 16.3.2.20/16-37 0x1BC ENDPTCOMPLETE—Endpoint complete 0x0000_0000 16.3.2.21/16-38 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-6 Freescale Semiconductor...
Page 949 Most of these registers are defined by the EHCI specification. Registers that are not defined by the EHCI specification are noted in their descriptions. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-7...
Page 950: Capability Registers Length (Caplength)
HCIVERSION register. Table 16-5. HCIVERSION Register Field Descriptions Bits Name Description 15–0 — EHCI revision number. Value is 0x0100 indicating version 1.0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-8 Freescale Semiconductor...
Page 951: Host Controller Structural Parameters (Hcsparams)
0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 1. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 952: Host Controller Capability Parameters (Hccparams)
BCD encoding of the device controller interface. The most-significant byte of the register represents a major revision and the least-significant byte is the minor revision. Figure 16-6 shows the DCIVERSION register. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-10 Freescale Semiconductor...
Page 953: Device Controller Capability Parameters (Dccparams)—Non-Ehci
Operational Registers The operational registers are comprised of dynamic control or status registers that may be read-only, read/write, or read/write-1-to-clear. The following sections define the operational registers. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-11...
Page 954: Usb Command Register (Usbcmd)
More information on the use of this bit is described in Section 16.9.2, “Device Operation.” — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-12 Freescale Semiconductor...
Page 955 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-13...
Page 956 Software clears certain bits in this register by writing a 1 to them (indicated by a w1c in the bit’s W cell). Offset 0x144 Access: Mixed — Reset All zeros ULPII — — Reset All zeros Figure 16-9. USB Status Register (USBSTS) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-14 Freescale Semiconductor...
Page 957 FS before connect, this bit is set at an interval of 1 msec during the prelude to the connect and chirp. Software writes a 1 to this bit to clear it. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-15...
Page 958: Usb Interrupt Enable Register (Usbintr)
The interrupts to software are enabled with the USB interrupt enable register, shown in Figure 16-10. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB status register MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-16 Freescale Semiconductor...
Page 959 System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[SEI]. 0 Disable 1 Enable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-17...
Page 960: Frame Index Register (Frindex)
125-µsec microframe). Figure 16-11 shows the USB frame index register. Offset 0x14C Access: Read/Write 14 13 — FRINDEX Reset All zeros Figure 16-11. USB Frame Index (FRINDEX) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-18 Freescale Semiconductor...
Page 961: Control Data Structure Segment Register (Ctrldssegment)
Note that this register is shared between the host and device mode functions. In host mode, it is the PERIODICLISTBASE register; in device mode, it is the DEVICEADDR register. See Section 16.3.2.7, “Device Address Register (DEVICEADDR)—Non-EHCI,” for more information. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-19...
Page 962 Table 16-16. DEVICEADDR Register Field Descriptions Bits Name Description 31–25 USBADR Device address. This field corresponds to the USB device address. 24–0 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-20 Freescale Semiconductor...
Page 963: Current Asynchronous List Address Register (Asynclistaddr)
Note that this register is shared between the host and device mode functions. In device mode, it is the ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See Section 16.3.2.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),” for more information. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-21...
Page 964: Master Interface Data Burst Size Register (Burstsize)—Non-Ehci
RXPBURST Programable RX burst length. This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. Must not be set to greater than 16. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-22...
Page 965: Transmit Fifo Tuning Controls Register (Txfilltuning)—Non-Ehci
Figure 16-17. Transmit FIFO Tuning Controls (TXFILLTUNING) Table 16-20 describes the transmit FIFO tuning controls register fields. Table 16-20. TXFILLTUNING Register Field Descriptions Bits Name Description 31–22 — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-23...
Page 966 USB operations. Also note that if the ULPI interface is not enabled, this register will always read zeros. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-24 Freescale Semiconductor...
Page 967 ULPI interface is operating in low power mode, serial mode, or carkit mode. The ULPI state can be determined by reading the sync state bit (ULPISS). If this bit is set, then the ULPI interface is running in MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 968: Configure Flag Register (Configflag)
In device mode, the USB DR controller does not support power control. Port control in device mode is only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-26...
Page 969 0 Allow the port to identify itself as high speed. 1 Force the port to only connect at full speed. This bit is not defined in the EHCI specification. This bit is for debugging purposes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-27...
Page 970 Port owner hand-off is not implemented in this design, therefore this bit is always 0. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-28...
Page 971 • This field is zero if Port Power (PP) is zero in host mode. Device mode: 1 Port in suspend state. 0 Port not in suspend state. Default. In device mode this bit is a read-only status bit. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-29...
Page 972 • The device port is always enabled. (This bit is zero.) 1 Port disabled. 0 No change. This field is zero if Port Power(PP) is zero. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-30 Freescale Semiconductor...
Page 973: On-The-Go Status And Control (Otgsc)—Non-Ehci
The status inputs are de-bounced using a 1-msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status inputs, or cause and OTG interrupt. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 974 Software must write a one to clear this bit. 1msS 1-millisecond timer interrupt status. Set once every millisecond. Software must write a one to clear this bit. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-32 Freescale Semiconductor...
Page 975 OTG termination. This bit must be set when the OTG device is in device mode. 1 Enable pulldown on DM 0 Disable pulldown on DM — Reserved, should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-33...
Page 976 SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See Section 16.8.3.5, “Control Endpoint Operation Model.” 1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW). 0 Setup lockouts on MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-34 Freescale Semiconductor...
Page 977: Endpoint Setup Status Register (Endptsetupstat)—Non-Ehci
This register is only used in device mode. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-35...
Page 978: Endpoint Flush Register (Endptflush)—Non-Ehci
Offset 0x1B4 Access: Read/Write 19 18 16 15 — FETB — FERB Reset All zeros Figure 16-25. Endpoint Flush (ENDPTFLUSH) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-36 Freescale Semiconductor...
Page 979: Endpoint Status Register (Endptstatus)—Non-Ehci
ENDPTFLUSH register. ETBR[2] (bit 18 of the register) corresponds to endpoint 2. Note that these bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-37...
Page 980: Endpoint Complete Register (Endptcomplete)—Non-Ehci
Transfer Descriptor, then this bit is set simultaneously with the USBINT. Writing a one will clear the corresponding bit in this register. ERCE[2] corresponds to endpoint 2. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-38...
Page 981: Endpoint Control Register 0 (Endptctrl0)—Non-Ehci
STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. 1 Endpoint stalled 0 Endpoint OK MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-39...
Page 982 STALL until this bit is either cleared by software or automatically cleared as above. 0 Endpoint OK 1 Endpoint stalled 15–8 — Reserved, should be cleared RX endpoint enable 0 Disabled 1 Enabled MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-40 Freescale Semiconductor...
Page 983: Snoop1 And Snoop2—Non-Ehci
Offset 0x400 (SNOOP1), 0x404 (SNOOP2) Access: Read/Write 19 20 26 27 Snoop Address — Snoop Enables Reset All zeros Figure 16-30. Snoop 1 and Snoop 2 (SNOOP n ) MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-41...
Page 984: Age Count Threshold Register (Age_Cnt_Thresh)—Non-Ehci
The AGE_CNT_THRESH is compared against the value of the aging counter during each clock cycle of the current transaction. If AGE_CNT_THRESH is equal to zero, priority state one is always chosen. If the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-42...
Page 985: Priority Control Register (Pri_Ctrl)—Non-Ehci
(PRI_CTRL) register sets the priority level for each of two priority states. The priority state is determined by the value programmed in the AGE_CNT_THRESH register and the number of csb_clk cycles that a particular transaction takes to complete. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-43...
Page 986: System Interface Control Register (Si_Ctrl)—Non-Ehci
When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller responds according to the values set in USBSTS[SEI] and USBINT[SEE]. 0 enable 1 disable MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-44 Freescale Semiconductor...
Page 987: Usb General Purpose Register (Control)—Non-Ehci
USB controller is exited from the low power by clearing the PORTSC[PHCD] bit. 0 Normal operation or Low Power mode waiting for wakeup event 1 Low power wakeup event has occurred MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-45...
Page 988 This prevents any start-up problems that otherwise could occur if the PHY and the controller take significantly different times to complete power-on reset. 1 Normal operation 0 Safe mode MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-46 Freescale Semiconductor...
Page 989: System Interface
The FIFO RAM controller is used for context information and to control FIFOs between the protocol engine and the DMA controller. These FIFOs decouple the system processor/memory bus requests from the extremely tight timing required by USB. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-47...
Page 990: Phy Interface
The data structures defined in this section are (from the host controller’s perspective) a mix of read-only and read/writable fields. The host controller must preserve the read-only fields on all data structure writes. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-48...
Page 991: Periodic Frame List
(for full-speed isochronous endpoints), or a queue head (used to support high-, full- and low-speed interrupt). System software should not place non-periodic schedule items into the periodic MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 992: Asynchronous List Queue Head Pointer
This structure is used only for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs must be aligned on a 32-byte boundary. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-50 Freescale Semiconductor...
Page 993: Next Link Pointer
10 siTD (split transaction isochronous transfer descriptor) 11 FSTN (frame span traversal node) Terminate 1 Link Pointer field is not valid. 0 Link Pointer field is valid. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-51...
Page 994: Itd Transaction Status And Control List
DWords 9–15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-52...
Page 995 01 One transaction to be issued for this endpoint per microframe 10 Two transactions to be issued for this endpoint per microframe 11 Three transactions to be issued for this endpoint per microframe MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-53...
Page 996: Split Transaction Isochronous Transfer Descriptor (Sitd)
10 siTD (split transaction isochronous transfer descriptor 11 FSTN (frame span traversal node) Terminate. 0 Link pointer is valid. 1 Link pointer field is not valid. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-54 Freescale Semiconductor...
Page 997: Sitd Endpoint Capabilities/Characteristics
An all zeros value in this field, in combination with existing periodic frame list has undefined results. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor...
Page 998: Sitd Transfer State
1 Do complete split. This value directs the host controller to issue a Complete split transaction to the endpoint when a match is encountered in the C-mask. Reserved, should be cleared. Bit reserved for future use and should be cleared. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-56 Freescale Semiconductor...
Page 999: Sitd Buffer Pointer List (Plus)
Table 16-52 describes the siTD back link pointer. Table 16-52. siTD Back Link Pointer Bits Name Description 31–5 Back Pointer A physical memory pointer to an siTD MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Freescale Semiconductor 16-57...
Page 1000: Queue Element Transfer Descriptor (Qtd)
Buffer Pointer (Page 4) 0000_0000_0000 0x1C Figure 16-40. Queue Element Transfer Descriptor (qTD) Host controller read/write; all others read-only. Queue element transfer descriptors must be aligned on 32-byte boundaries. MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 16-58 Freescale Semiconductor...

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Freescale Semiconductor MPC8313E Family Reference Manual

Table of Contents

Figures

Chapter 1

Chapter 14 Security Engine

Chapter 9

Chapter 8 Integrated Programmable Interrupt Controller (Ipic)

Chapter 2 Signal Descriptions

Chapter 4

Chapter 5

Chapter 6 Coherent System Bus Overview

Chapter 7

Chapter 10

Chapter 11 Sequencer

Chapter 12

Chapter 13

Chapter 15 External Signals Description

Chapter 16

Chapter 17 C Interfaces

Chapter 18

Chapter 19

Chapter 20 Jtag External Signal Descriptions

Chapter 21

Appendix A Revision History

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