Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 513

• Read data to buffer RAM once waited on ready—RBW. This instruction first polls the LFRB pin,
waiting for it to go high, before proceeding with a read to buffer as described for the RB instruction.
Sampling and time-outs for polling the LFRB pin follow the behavior of CWn instructions.
• Read data/status to MDR once waited on ready—RSW. This instruction first polls the LFRB pin,
waiting for it to go high, before proceeding with a status read to MDR as described for the RS
instruction. Sampling and time-outs for polling the LFRB pin follow the behavior of CWn
instructions.
10.4.3.2.5 FCM Data Write Instructions
Data write instructions assert LFWE repeatedly (with LFCLE and LFALE both negated) to transfer one or
more bytes of write data to the NAND Flash EEPROM. Data write instructions are distinguished by their
data source:
• Write data from FCM buffer RAM—WB. This instruction writes FBCR[BC] bytes of data from
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
stored in the appropriate FECC
FMR[ECCM]. If the value of FBCR[BC] takes the write pointer beyond the end of the spare region
in the buffer, the value of data written by FCM is undefined.
• Write data/status from MDR—WS. This instruction asserts LFWE exactly once to write one byte
(8-bit port size) of data taken from the next AS field of MDR. Attempts to write beyond four bytes
of MDR has the effect of writing zeros. The MDR write pointer is independent of the MDR read
pointer used by RS and RSW instructions.
10.4.3.3 FCM Signal Timing
If BR [MSEL] selects the FCM, the attributes for the memory cycle are taken from OR
n
include the CSCT, CST, CHT, RST, SCY, TRLX, and EHTR fields.
10.4.3.3.1 FCM Chip-Select Timing
The timing of LCSn assertion in FCM mode is illustrated by the timing diagram in
asserted immediately following LALE negation, and remains asserted until the last instruction in FIR has
completed. The delay, t
instruction is controlled by ORn[CSCT] and ORn[TRLX], as shown in
be set in accordance with the NAND Flash EEPROM chip-select to WE set-up time specification.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
registers and spare region in accordance with the setting of
n
, between LCSn assertion and commencement of the first NAND Flash
CSCT
Table 10-35. FCM Chip-Select to First Command Timing
ORn[TRLX] ORn[CSCT] LCS n to First Command Delay
0 0
0 1
1 0
1 1
Table
1 LCLK clock cycle
4 LCLK clock cycles
2 LCLK clock cycles
8 LCLK clock cycles
Enhanced Local Bus Controller
. These attributes
n
Figure 10-45. LCSn is
10-35. ORn[CSCT] should
10-65