Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 717

14.6.6 Interrupts
The SEC generates a single interrupt to the MPC8313E programmable interrupt controller. The user
allows interrupts from the SEC to be reported to the CPU by setting the mask bit in SIMSR_H[SEC].
The user can control which events cause an interrupt by configuring the SEC interrupt mask register
(IMR). These events are:
• Done (of a channel or an execution unit)
• Error (of a channel or an execution unit)
When the user detects an interrupt request from the SEC, it should further read the SEC interrupt status
register (ISR) to determine the source of that interrupt. To clear an interrupt, the user should write 1 to the
bits in the SEC interrupt clear register (ICR) corresponding to the pending ISR bits.
Events may be further masked per channel by setting or clearing the related fields in the crypto-channel
configuration registers. It is suggested that the user leave channel interrupts unmasked, while masking the
interrupts from the EUs. Errors or Done signals coming from the EUs eventually cause the channel to
signal an error or Done interrupt. Clearing an interrupt before eliminating the condition which caused the
interrupt will cause the interrupt to be asserted again a few cycles later.
14.7 Power Saving Mode
The SEC can be disabled by clearing SCCR[ENCCM]. See
Register (SCCR)," for more information.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Section 4.5.2.3, "System Clock Control
Security Engine (SEC) 2.2
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