Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 912

Enhanced Three-Speed Ethernet Controllers
Table 15-166 describes the shared signals of the MII interface.
eTSEC Signals
MDIO
MDC
ECGTX_CLK125
Sum
Table 15-167 describes the register initializations required to configure the eTSEC in MII mode.
(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY through
Writing to MII Mgmt Control with 16-bit data intended for the external PHY register,
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-194
Table 15-166. Shared MII Signals
No. of
I/O MII Signals
Signals
I/O 1 MDIO
O 1 MDC
I 1 not used
Table 15-167. MII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2, for MII, half duplex operation.
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
(This example has Statistics Enable = 1)
Initialize MAC Station Address,
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Initialize MAC Station Address,
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
Set station address to 02_60_8C_87_65_43, for example.
Reset the management interface.
MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0111]
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
the Management interface (overrides configuration signals of the PHY).
MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]
Perform an MII Mgmt write cycle to the external PHY
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]
No. of
I/O
Signals
I/O 1
O 1
I 0
Sum
Set Soft_Reset,
Set I/F Mode bit,
Function
Management interface I/O
Management interface clock
Reference clock
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