Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 638

PCI Bus Interface
PCI_FRAME and PCI_IRDY are negated. Special cycles terminate with a master-abort. (In the special
cycle case, the received-master-abort bit in the configuration status register is not set.)
The address phase contains no valid information other than the command field. Even though there is no
explicit address, the address/data lines are driven to a stable state and parity is generated. During the data
phase, the address/data lines contain the message type and an optional data field. The message is encoded
on the sixteen least-significant bits (AD[15:0]). The data field is encoded on AD[31:16]. When running a
special cycle, the message and data are valid on the first clock PCI_IRDY is asserted.
When the PCI_CONFIG_ADDRESS register is written with a value so that the bus number matches the
bridge bus, the device number is all ones, the function number is all ones, and the register number is zero.
The next time the PCI_CONFIG_DATA register is accessed, the PCI controller executes either a special
cycle or an interrupt acknowledge command. When the PCI_CONFIG_DATA register is written, the PCI
controller generates a special cycle encoding on the command/byte enable lines during the address phase
and drives the data from the PCI_CONFIG_DATA register onto the address/data lines during the first data
phase.
If the bus number field of the PCI_CONFIG_ADDRESS does not match one of the PCI controller bus
numbers, the PCI controller passes the write to PCI_CONFIG_DATA through to the PCI bus as a type 1
configuration cycle as it does any other time the bus number field does not match.
Address
Message Type
(AD[15–0])
0x0000 SHUTDOWN (SLEEP) Indicates the processor is entering its most power saving mode
0x0001 HALT (DOZE)
0x0002– —
0xFFFF
13.4.4.7 Interrupt Acknowledge
When the PCI_CONFIG_ADDRESS register is written with a value such that the bus number is 0x00, the
device number is all ones, the function number is all ones, and the register number is zero, the next time
the PCI_CONFIG_DATA register is accessed the PCI controller does either a special cycle command or
an interrupt acknowledge command. When the PCI_CONFIG_DATA register is read, the PCI controller
generates an interrupt acknowledge command encoding on the command/byte enable lines during the
address phase. During the address phase, AD[31:0] do not contain a valid address but are driven with stable
data and valid parity (PCI_PAR). During the data phase, the byte enable signals determine which bytes are
involved in the transaction. The interrupt vector must be returned when PCI_TRDY is asserted.
An interrupt acknowledge transaction can also be issued on the PCI bus by reading from the
PCI_INT_ACK register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-56
Table 13-46. Special Cycle Commands
Indicates the processor is entering a power save mode where address decoding is still
available
Reserved for future commands
Description
Freescale Semiconductor