Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 834

Enhanced Three-Speed Ethernet Controllers
Offset eTSEC1:0x2_4E10
0
R
W
Reset
16
R
W
Reset
Table 15-114 describes the fields of the TMR_PEMASK register fields for the timer.
Bits Name
0–21 — Reserved
22 TXP2EN Transmit PTP packet event 2 enable
23 TXP1EN Transmit PTP packet event 1 enable
24–30 — Reserved
31 RXPEN Receive PTP packet event enable
15.5.3.10.6 Timer Status Register (TMR_STAT)
This register requires the eTSEC filer to be enabled (via RCTRL[FILREN]). When eTSEC generates an
interrupt based on the timestamp event for a received packet, the queue ID which the incoming packet will
be sent to is captured in this register. This register update is synchronized with the RXF interrupt of the
corresponding received packet. Writing 1 to any bit of this register clears it.
definition for the TMR_STAT register.
Offset eTSEC1:0x2_4E14
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-116
21
— TXP2EN TXP1EN
Figure 15-108. TMR_PEMASK Register Definition
Table 15-114. TMR_PEMASK Register Field Descriptions
—
Table 15-115. TMR_STAT Register Definition
—
All zeros
22 23 24
All zeros
Description
All zeros
Access: Read/Write
30
— RXPEN
Figure 15-115 describes the
Access: Mixed
25 26
STAT_VEC
Freescale Semiconductor
15
31
31