DDR memory indicating the write to PCI has completed. An external PCI master may misread the flag
ahead of the actual write transaction's completion on the PCI bus.
13.1.1
Features
The PCI controller includes the following features:
•
PCI specification revision 2.3 compliant
•
32-bit PCI interface support
•
Host and agent mode support
•
PCI bus power management unit
•
Supports accesses to all PCI address spaces
•
64-bit dual-address cycle (DAC) support (as a target only)
•
Internal configuration registers accessible from PCI
•
On-chip arbitration supporting three masters on PCI
•
Arbiter supports two-level priority request/grant signal pairs
•
Supports PCI-to-memory and memory-to-PCI streaming
•
Memory prefetching of PCI read accesses and support for delayed read transactions
•
Supports posting of processor-to-PCI and PCI-to-memory writes
•
Supports selectable snooping for inbound transactions
•
Address translation units for address mapping between host and peripheral
•
Supports parity
•
PCI 3.3-V compatible
13.1.2
Modes of Operation
PCI controller modes of operation are determined at reset by the reset configuration word high (RCWH)
as described in
Section 4.3.2, "Reset Configuration
Parameter
Host/agent configuration
PCI arbiter enable
13.1.2.1
Host/Agent Mode Configuration
The PCI controller can function as either a PCI host bridge (referred to as host mode) or a peripheral device
on the PCI bus (referred to as agent mode). Note that host/agent mode selection is determined at power-up
as summarized
inSection 4.3.2.2.1, "PCI Host/Agent Configuration."
When the device powers up in host m ode, all inbound configuration accesses are ignored (and thus master
aborted). When the device powers up in agent mode, it acknowledges inbound configuration accesses.
Note that in PCI agent mode, the PCI controller ignores all PCI memory accesses except those to the
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 13-1. PCI Controller Modes
Selects between host and agent mode for the PCI interface.
Enables the on-chip PCI bus arbiter
Words."
Table 13-1
summarizes these modes.
Description
PCI Bus Interface
Section/Page
4.3.2.2.1/4-16
4.3.2.2/4-14
13-3