Table 3-1. MPC8313E Signal Reference by Functional Block (continued)
Name
SD_REF_CLK
SD_REF_CLK
TXA
TXA
TXB
TXB
XCOREVDD[0:2]
XCOREVSS[0:2]
XPADVDD[0:1]
XPADVSS[0:1]
LAD[0:15]
LA[16:25]
LA[0:4]
LA[5]
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Functional
Description
Block
SerDes PLL
SGMII PHY
reference clock
SerDes PLL
SGMII PHY
reference clock
(complement)
Serial transmitter,
SGMII PHY
lane A, positive data
Serial transmitter,
SGMII PHY
lane A, negative
data (complement)
Serial transmitter,
SGMII PHY
lane B, positive data
Serial transmitter,
SGMII PHY
lane B, negative
data (complement)
SerDes transceiver
SGMII PHY
core supply
SerDes transceiver
SGMII PHY
core ground
SerDes transceiver
SGMII PHY
pad supply
SerDes transceiver
SGMII PHY
pad ground
LBC address/data
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
LBC port address
eLBC
eLBC port address
eLBC
No. of
Table/
I/O
Signals
Page
1
I
15-2/15-8
1
I
15-2/15-8
1
O
15-2/15-8
1
O
15-2/15-8
1
O
15-2/15-8
1
O
15-2/15-8
2
3
PWR
15-2/15-8
3
GND
15-2/15-8
2
2
PWR
15-2/15-8
2
GND
15-2/15-8
16
I/O
10-2/10-5
10
O
10-2/10-5
5
I/O
10-2/10-5
1
I/O
10-2/10-5
1
I/O
10-2/10-5
1
I/O
10-2/10-5
1
I/O
10-2/10-5
1
I/O
10-2/10-5
1
O
10-2/10-5
1
O
10-2/10-5
1
O
10-2/10-5
1
O
10-2/10-5
Signal Descriptions
Alternate
Function(s)
—
—
—
—
—
—
—
—
—
—
—
—
MSRCID[0:4]/
GPIO[0:4]
MDVAL/GPIO5
GPIO6
GPIO7/
TSEC_1588_TRIG2
GPIO13/
TSEC_1588_ALARM1
GPIO14/
TSEC_1588_PP3
TSEC_1588_CLK
TSEC_1588_GCLK
TSEC_1588_PP1
TSEC_1588_PP2
3-9