Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 452

Enhanced Local Bus Controller
10.1.3.2 Source ID Debug Mode
The eLBC provides the ID of a transaction source on external device pins. When those pins are selected,
the 5-bit internal ID of the current transaction source appears on LSRCID[0:4] whenever valid address or
data is available on the eLBC external pins. The reserved value of 0x1F, which indicates invalid address
or data, appears on the source ID pins at all other times. The combination of a valid source ID (any value
except 0x1F) and the value of external address latch enable (LALE) and data valid (LDVAL) facilitate
capturing useful debug data as follows:
• If a valid source ID is detected on LSRCID[0:4] and LALE is asserted, a valid full 26-bit address
may be latched from LAD[0:15] and combined with LA[16:25].
• If a valid source ID is detected on LSRCID[0:4] and LDVAL is asserted, valid data may be latched
from LAD.
The LSRCID[0:4] and LDVAL signals are multiplexed with other functions sharing the same external
pins. Refer to Chapter 3, "Signal Descriptions," and Chapter 4, "Reset, Clocking, and Initialization,"
learn how to enable the LSRCID/LDVAL pins.
10.2 External Signal Descriptions
Table 10-1 contains a list of external signals related to the eLBC and summarizes their function. The table
also shows the reset state of all external signals during assertion of HRESET. For more information on the
use of some of these signals as reset configuration signals on the device, see "Power on Reset Flow."
Alternate
Name
Function(s)
LALE —
LCS[0:3] —
LWE0/ LWE0
LFWE/
LFWE
LBS0
LBS0
LWE1/ LWE
LBS1
LBS
LGPL0/ LGPL0
LFCLE
LFCLE
LGPL1/ LGPL1
LFALE
LFALE
LOE/ LOE
LGPL2/
LFRE
LFRE
LGPL2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-4
Table 10-1. Signal Properties—Summary
Mode
— External address latch enable
— Chip selects 0–3
GPCM Write enable 0
FCM Write enable
UPM Byte (lane) select 0
GPCM Write enable 1
UPM Byte (lane) select 1
UPM General purpose line 0
FCM Flash command latch enable
UPM General purpose line 1
FCM Flash address latch enable
GPCM Output enable
FCM Flash read enable
UPM General purpose line 2
Descriptions
to
No. of Reset State
I/O
Signals (Outputs)
1 O Reset_cfg
4 O Reset_cfg
1 O Reset_cfg
1
1
1 O Reset_cfg
1
1 O Reset_cfg
1
1 O Reset_cfg
1
1 O
1
1
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