Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 135

Chapter 3
Signal Descriptions
This chapter describes the external signals of the device. It is organized into the following sections:
• Overview of signals and cross references for signals that serve multiple functions, including two
lists: one ordered by functional block and one alphabetical.
• List of reset configuration signals
• List of output signal states at reset
A bar over a signal name indicates that the signal is active low, such as
IRQ_OUT (interrupt out). Active-low signals are referred to as asserted
(active) when they are low and negated when they are high. Signals that are
not active low, such as IRQ (interrupt input), are referred to as asserted when
they are high and negated when they are low.
Internal signals throughout this document are shown as lower case and in
italics. For example, sys_logic_clk is an internal signal. These are
referenced only as necessary for understanding of the external functionality
of the device.
3.1 Signals Overview
The signals are grouped as follows:
• DDR memory interface signals
• PCI interface signals
• DUART interface signals
2
• I C interface signals
• Serial peripheral interface signals
• Ethernet management interface signals
• eTSEC1 and USB interface signals
• eTSEC1 and 1588 interface signals
• eTSEC2 interface signals
• SerDes interface signals
Figure 3-1 and Figure 3-2
to the MPC8313E Integrated Processor Hardware Specifications for a pinout diagram showing pin
numbers and a listing of all the electrical and mechanical specifications.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
show the external signals of the device and how the signals are grouped. Refer
NOTE
• Enhanced local bus interface signals
• USB PHY signals
• Global timers/USB interface signals
• PIC interface signals
• SPI, JTAG, PMC, configuration, system
control signals
• SGMII PHY interface signals
• Clock signals
3-1