Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 667

Bits Name
55 DSE Data size error (DSE): A value was written to the DEU data size register that is not a multiple of 64 bits.
0 No error detected
1 Data size error
56 ME Mode error. An illegal value was detected in the mode register. Note: writing to reserved bits in mode
register is likely source of error.
0 No error detected
1 Mode error
57 AE Address error. An illegal read or write address was detected within the DEU address space.
0 No error detected
1 Address error
58 OFE Output FIFO error. The DEU output FIFO was detected non-empty upon write of DEU data size register.
0 No error detected
1 Output FIFO non-empty error
59 IFE Input FIFO error. The DEU input FIFO was detected non-empty upon generation of DONE interrupt.
0 No error detected
1 Input FIFO non-empty error
60 IFU Input FIFO underflow. The DEU input FIFO has been read while empty.
0 No error detected
1 Input FIFO has had underflow error
61 IFO Input FIFO overflow. The DEU input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
62 OFU Output FIFO underflow. The DEU output FIFO has been read while empty.
0 No error detected
1 Output FIFO has underflow error
63 OFO Output FIFO overflow. The DEU output FIFO has been pushed while full.
0 No error detected
1 Output FIFO has overflowed
14.4.1.7 DEU Interrupt Control Register (DEUICR)
The DEU interrupt control register (DEUICR), shown in
errors. For a given error (as defined in
the corresponding bit in the DEUICR is set, the error is ignored; no bit is set in the DEUISR, and no error
interrupt occurs. If the corresponding bit is not set, then upon detection of an error, the DEUISR is updated
to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt
processing.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 14-15. DEUISR Field Descriptions (continued)
is not a limit to data input. When operated through host-controlled access, the DEU cannot accept
FIFO inputs larger than 256 bytes without overflowing.
Section 14.4.1.6, "DEU Interrupt Status Register
Description
Figure 14-13, controls the result of detected
Security Engine (SEC) 2.2
(DEUISR)"), if
14-25