Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 30

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Number
16.3.2.18 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI......................... 16-35
16.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI .................................... 16-36
16.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI ................................. 16-36
16.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI..................... 16-37
16.3.2.22 Endpoint Control Register 0 (ENDPTCTRL0)—Non-EHCI .............................. 16-38
16.3.2.23 Endpoint Control Register n (ENDPTCTRLn)—Non-EHCI .............................. 16-39
16.3.2.24 SNOOP1 and SNOOP2—Non-EHCI.................................................................. 16-40
16.3.2.25 Age Count Threshold Register (AGE_CNT_THRESH)—Non-EHCI ............... 16-41
16.3.2.26 Priority Control Register (PRI_CTRL)—Non-EHCI.......................................... 16-42
16.3.2.27 System Interface Control Register (SI_CTRL)—Non-EHCI.............................. 16-43
16.3.2.28 USB General Purpose Register (CONTROL)—Non-EHCI................................ 16-43
16.4 Functional Description................................................................................................. 16-45
16.4.1 System Interface ...................................................................................................... 16-45
16.4.2 DMA Engine............................................................................................................ 16-46
16.4.3 FIFO RAM Controller ............................................................................................. 16-46
16.4.4 PHY Interface .......................................................................................................... 16-46
16.5 Host Data Structures .................................................................................................... 16-47
16.5.1 Periodic Frame List.................................................................................................. 16-47
16.5.2 Asynchronous List Queue Head Pointer.................................................................. 16-49
16.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 16-49
16.5.3.1 Next Link Pointer ................................................................................................ 16-50
16.5.3.2 iTD Transaction Status and Control List ............................................................. 16-51
16.5.3.3 iTD Buffer Page Pointer List (Plus) .................................................................... 16-51
16.5.4 Split Transaction Isochronous Transfer Descriptor (siTD)...................................... 16-53
16.5.4.1 Next Link Pointer ................................................................................................ 16-53
16.5.4.2 siTD Endpoint Capabilities/Characteristics......................................................... 16-53
16.5.4.3 siTD Transfer State .............................................................................................. 16-54
16.5.4.4 siTD Buffer Pointer List (Plus)............................................................................ 16-55
16.5.4.5 siTD Back Link Pointer ....................................................................................... 16-56
16.5.5 Queue Element Transfer Descriptor (qTD) ............................................................. 16-56
16.5.5.1 Next qTD Pointer................................................................................................. 16-57
16.5.5.2 Alternate Next qTD Pointer................................................................................. 16-57
16.5.5.3 qTD Token ........................................................................................................... 16-58
16.5.5.4 qTD Buffer Page Pointer List .............................................................................. 16-61
16.5.6 Queue Head.............................................................................................................. 16-62
16.5.6.1 Queue Head Horizontal Link Pointer .................................................................. 16-62
16.5.6.2 Endpoint Capabilities/Characteristics.................................................................. 16-63
16.5.6.3 Transfer Overlay .................................................................................................. 16-65
16.5.7 Periodic Frame Span Traversal Node (FSTN)......................................................... 16-66
16.5.7.1 FTSN Normal Path Pointer.................................................................................. 16-67
16.5.7.2 FSTN Back Path Link Pointer ............................................................................. 16-67
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor