Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 964

Universal Serial Bus Interface
Table 16-27. ENDPTPRIME Register Field Descriptions (continued)
Bits Name
15–3 — Reserved, should be cleared.
2–0 PERB Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a
receive operation in order to respond to a USB OUT transaction. Software should write a one to the
corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB[2] corresponds
to endpoint 2.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
16.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
Offset 0x2_31B4
31
R
W
Reset
Bits Name
31–19 — Reserved, should be cleared.
18–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[2] (bit 18 of the register) corresponds to endpoint 2.
15–3 — Reserved, should be cleared.
2–0 FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[2]
corresponds to endpoint 2.
16.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
Offset 0x2_31B8
31
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-36
19 18
— FETB
Figure 16-25. Endpoint Flush (ENDPTFLUSH)
Table 16-28. ENDPTFLUSH Register Field Descriptions
21 18
ETBR
—
Figure 16-26. Endpoint Status (ENDPTSTATUS)
Description
16 15
All zeros
Description
16 15
All zeros
Access: Read/Write
3
—
Access: Read only
3
—
Freescale Semiconductor
2 0
FERB
2 0
ERBR